Bechir Ayari

According to our database, Bechir Ayari authored at least 8 papers between 1994 and 2000.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2000

Test Cycle Count Reduction in a Parallel Scan BIST Environment.

Bechir Ayari, Prab Varma

J. Electron. Test., 2000

1996

Testing of embedded A/D converters in mixed-signal circuit.

Naim Ben-Hamida, Bechir Ayari, Bozena Kaminska

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995

Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits.

Samir Lejmi, Bozena Kaminska, Bechir Ayari

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Synthesis and Retiming for the Pseudo-Exhaustive BIST of Synchronous Sequential Circuits.

Samir Lejmi, Bozena Kaminska, Bechir Ayari

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Retiming for BIST-Sequential Circuits.

Samir Lejmi, Bozena Kaminska, Bechir Ayari

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

BDD-FTEST: Fast, Backtrack-Free Test Generator Based on Binary Decision Diagram Representation.

Bechir Ayari, Bozena Kaminska

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Automatic test vector generation for mixed-signal circuits.

Bechir Ayari, Naim Ben-Hamida, Bozena Kaminska

Proceedings of the 1995 European Design and Test Conference, 1995

1994

A new dynamic test vector compaction for automatic test pattern generation.

Bechir Ayari, Bozena Kaminska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994