Bastien Deveautour

According to our database, Bastien Deveautour authored at least 26 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Special Session: Reliability Assessment Recipes for DNN Accelerators.

Mohammad Hasan Ahmadilivani, Alberto Bosio, Bastien Deveautour, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Maksim Jenihhin, Angeliki Kritikakou, Robert Limas Sierra, Salvatore Pappalardo, Jaan Raik, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Mahdi Taheri, Marcello Traiola

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Artificial neural network-based solution for PSP MOSFET model card extraction.

Alba Ordonez Rodriguez, Fabien Gilibert, Francois Paolini, Pascal Urard, Roberto Guizzetti, John Samuel, Remy Cellier, Lioua Labrak, Bastien Deveautour

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

3D VNWFET-Based Standard Cell Library Design Flow: from Circuit and Physical Design to Logic Synthesis.

Sara Mannaa, Cédric Marchand, Damien Deleruyelle, Bastien Deveautour, Alberto Bosio, Christoph Lenz, Oskar Baumgartner, Ian O'Connor

Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

Heterogeneous Approximation of DNN HW Accelerators based on Channels Vulnerability.

Natalia Cherezova, Salvatore Pappalardo, Mahdi Taheri, Mohammad Hasan Ahmadilivani, Bastien Deveautour, Alberto Bosio, Jaan Raik, Maksim Jenihhin

Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

Approximate Fault-Tolerant Neural Network Systems.

Marcello Traiola, Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio, Sepide Saeedi, Alessio Carpegna, Anil Bayram Gogebakan, Enrico Magliano, Alessandro Savino

Proceedings of the IEEE European Test Symposium, 2024

Reliable and Efficient hardware for Trustworthy Deep Neural Networks.

Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio

Proceedings of the IEEE International Conference on Design, 2024

How Systolic Array Dataflow impacts on the resilience to hardware faults.

Salvatore Pappalardo, Bastien Deveautour, Alberto Bosio

Proceedings of the IEEE International Conference on Design, 2024

SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators.

Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio

Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation.

Ian O'Connor, Sara Mannaa, Alberto Bosio, Bastien Deveautour, Damien Deleruyelle, Tetiana Obukhova, Cédric Marchand, Jens Trommer, Çigdem Çakirlar, Bruno Neckel Wesling, Thomas Mikolajick, Oskar Baumgartner, Mischa Thesberg, David Pirker, Christoph Lenz, Zlatan Stanojevic, Markus Karner, Guilhem Larrieu, Sylvain Pelloquin, Konstantinous Moustakas, Jonas Müller, Giovanni Ansaloni, Alireza Amirshahi, David Atienza, Jean-Luc Rouas, Leila Ben Letaifa, Georgeta Bordeall, Charles Brazier, Chhandak Mukherjee, Marina Deng, Yifan Wang, Marc François, Houssem Rezgui, Reveil Lucas, Cristell Maneux

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

A Fault Injection Framework for AI Hardware Accelerators.

Salvatore Pappalardo, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio

Proceedings of the 24th IEEE Latin American Test Symposium, 2023

Energy-efficient Computation-In-Memory Architecture using Emerging Technologies.

Rajendra Bishnoi, Sumit Diware, Anteneh Gebregiorgis, Simon Thomann, Sara Mannaa, Bastien Deveautour, Cédric Marchand, Alberto Bosio, Damien Deleruyelle, Ian O'Connor, Hussam Amrouch, Said Hamdioui

Proceedings of the International Conference on Microelectronics, 2023

Input-aware accuracy characterization for approximate circuits.

Ali Piri, Salvatore Pappalardo, Salvatore Barone, Mario Barbareschi, Bastien Deveautour, Marcello Traiola, Ian O'Connor, Alberto Bosio

Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator.

Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Resilience-Performance Tradeoff Analysis of a Deep Neural Network Accelerator.

Salvatore Pappalardo, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022

Exploiting Approximate Computing for Efficient and Reliable Convolutional Neural Networks.

Alberto Bosio, Bastien Deveautour, Ian O'Connor

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope?

Cristiana Bolchini, Alberto Bosio, Luca Cassano, Bastien Deveautour, Giorgio Di Natale, Antonio Miele, Ian O'Connor, Elena-Ioana Vatajelu

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

Input-Aware Approximate Computing.

Ali Piri, Sepide Saeedi, Mario Barbareschi, Bastien Deveautour, Stefano Di Carlo, Ian O'Connor, Alessandro Savino, Marcello Traiola, Alberto Bosio

Proceedings of the IEEE International Conference on Automation, 2022

Test and Reliability of Approximate Hardware.

Marcello Traiola, Bastien Deveautour, Alberto Bosio, Patrick Girard, Arnaud Virazel

Proceedings of the Approximate Computing, 2022

2021

Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing.

Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Emerging Computing Devices: Challenges and Opportunities for Test and Reliability^*.

Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels

Proceedings of the 26th IEEE European Test Symposium, 2021

2020

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits.

Bastien Deveautour, Arnaud Virazel, Patrick Girard, Valentin Gherman

J. Electron. Test., 2020

Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs.

Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssade, Arnaud Virazel

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction.

Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard

Proceedings of the IEEE European Test Symposium, 2020

2018

Is aproximate computing suitable for selective hardening of arithmetic circuits?

Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits.

Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda

J. Electron. Test., 2017

2016

A low-cost susceptibility analysis methodology to selectively harden logic circuits.

Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda

Proceedings of the 21th IEEE European Test Symposium, 2016