Bastian Haetzer

According to our database1, Bastian Haetzer authored at least 9 papers between 2009 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2014
Asynchronous parallel simulation with transaction events.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

A comparison of parallel systemc simulation approaches at RTL.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

2013
Systemc transaction level modeling with transaction events.
Proceedings of the 2013 Forum on specification and Design Languages, 2013

2011
Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs.
Int. J. Reconfigurable Comput., 2011

Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

A case study on message-based discrete event simulation for Transaction Level Modeling.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Practical embedded systems engineering syllabus for graduate students with multidisciplinary backgrounds.
Proceedings of the 6th Workshop on Embedded Systems Education, 2011

2010
Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/ Virtex II-Pro FPGAs: A Case Study of Distributed Power Management.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

2009
An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing.
Int. J. Reconfigurable Comput., 2009


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