Basireddy Karunakar Reddy
Orcid: 0000-0001-9755-1041
According to our database1,
Basireddy Karunakar Reddy
authored at least 21 papers
between 2013 and 2020.
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Bibliography
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Computers, 2020
IEEE Des. Test, 2020
2019
Predictive Thermal Management for Energy-Efficient Execution of Concurrent Applications on Heterogeneous Multicores.
IEEE Trans. Very Large Scale Integr. Syst., 2019
EdgeCoolingMode: An Agent Based Thermal Management Mechanism for DVFS Enabled Heterogeneous MPSoCs.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
2018
IEEE Trans. Multi Scale Comput. Syst., 2018
J. Low Power Electron., 2018
Cut-less Technology Mapping Using Shannon Factor Graph with on-the-fly Size Reduction.
J. Low Power Electron., 2018
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Energy-Efficient Run-Time Mapping and Thread Partitioning of Concurrent OpenCL Applications on CPU-GPU MPSoCs.
ACM Trans. Embed. Comput. Syst., 2017
Learning-Based Run-Time Power and Energy Management of Multi/Many-Core Systems: Current and Future Trends.
J. Low Power Electron., 2017
Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing.
J. Low Power Electron., 2017
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
2014
A Novel Integrated Circuit Design Methodology Using Dynamic Library Concept with Reduced Non-Recurring Engineering Cost and Time-to-Market.
J. Low Power Electron., 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
A New Dynamic Library Based IC Design Automation Methodology Using Functional Symmetry with NPN Class Representation Approach to Reduce NRE Costs and Time-to-Market.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
Effect of Constant One and Zero, Shared and Non-decomposed Nodes on Runtime and Graph Size of the Shannon Factor Graph (SFG).
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
A new VLSI IC design automation methodology with reduced NRE costs and time-to-market using the NPN class Representation and functional symmetry.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
A Novel Physical Synthesis Methodology in the VLSI Design Automation by Introducing Dynamic Library Concept.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
A Novel and Unified Digital IC Design and Automation Methodology with Reduced NRE Cost and Time-to-Market.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013