Bashir M. Al-Hashimi

Lajos Hanzo

Proceedings of the 2015 IEEE International Conference on Communications, 2015

Adaptive Energy Minimization of OpenMP Parallel Applications on Many-Core Systems.

[BibT_eX]

[DOI]

Proceedings of the 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2015

Diagnosis of power switches with power-distribution-network consideration.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE European Test Symposium, 2015

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE European Test Symposium, 2015

Workload uncertainty characterization and adaptive frequency scaling for energy minimization of embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Active Mode Subclock Power Gating.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Delay Test for Diagnosis of Power Switches.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive Open and Bridge Defects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Learner-battery interaction in energy-aware learning multimedia systems.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Mobile and Ubiquitous Multimedia, 2014

Energy-Aware Streaming Multimedia Adaptation: An Educational Perspective.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Advances in Mobile Computing and Multimedia, 2014

Clock-modulation based watermark for protection of embedded processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Advanced SIMD: Extending the reach of contemporary SIMD architectures.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Reinforcement Learning-Based Inter- and Intra-Application Thermal Optimization for Lifetime Improvement of Multicore Systems.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

High Quality Testing of Grid Style Power Gating.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Energy-Conscious Turbo Decoder Design: A Joint Signal Processing and Transmit Energy Reduction Approach.

[BibT_eX]

[DOI]

IEEE Trans. Veh. Technol., 2013

A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Analysis of voltage- and clock-scaling-induced timing errors in stochastic LDPC decoders.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE Wireless Communications and Networking Conference (WCNC), 2013

Tunable vibration energy harvester.

[BibT_eX]

[DOI]

Proceedings of the 1st International Workshop on Energy Neutral Sensing Systems, 2013

Applying of Quality of Experience to system optimisation.

[BibT_eX]

[DOI]

Sascha Bischoff

Andreas Hansson

Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Hardware reliability of embedded systems: Are we there yet?

[BibT_eX]

[DOI]

Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Content-Aware Power Saving Multimedia Adaptation for Mobile Learning.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on Next Generation Mobile Apps, 2013

Energy-Aware Adaptation of Educational Multimedia in Mobile Learning.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Advances in Mobile Computing & Multimedia, 2013

Impact of PVT variation on delay test of resistive open and resistive bridge defects.

[BibT_eX]

[DOI]

Shida Zhong

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

A survey of multi-source energy harvesting systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

DoE-based performance optimization of energy management in sensor nodes powered by tunable energy-harvesters.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

MALEC: a multiple access low energy cache.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Photovoltaic Sample-and-Hold Circuit Enabling MPPT Indoors for Low-Power Systems.

[BibT_eX]

[DOI]

Alex S. Weddell

Geoff V. Merrett

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

An Explicit Linearized State-Space Technique for Accelerated Simulation of Electromagnetic Vibration Energy Harvesters.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Low-Energy Standby-Sparing for Hard Real-Time Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

System-level design optimization of reliable and low power multiprocessor system-on-chip.

[BibT_eX]

[DOI]

Jeffrey S. Reeve

Microelectron. Reliab., 2012

dRail: A Novel Physical Layout Methodology for Power Gated Circuits.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Enabling the discovery of Adaptive Learning Resources for Mobile Learner.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Mobile and Contextual Learning, 2012

RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Response-surface-based design space exploration and optimisation of wireless sensor nodes with tunable energy harvesters.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Accelerators and emulators: Can they become the platform of choice for hardware verification?

[BibT_eX]

[DOI]

Ronny Morad

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Coordinate Rotation Based Low Complexity N-D FastICA Algorithm and Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2011

Algorithm and Architecture for N-D Vector Cross-Product Computation.

[BibT_eX]

[DOI]

Amit Acharyya

IEEE Trans. Signal Process., 2011

Accurate Supercapacitor Modeling for Energy Harvesting Wireless Sensor Nodes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects.

[BibT_eX]

[DOI]

Shida Zhong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2011

A low-power, distributed, pervasive healthcare system for supporting memory.

[BibT_eX]

[DOI]

Proceedings of the First ACM MobiHoc Workshop on Pervasive Wireless Healthcare, 2011

Investigation into voltage and process variation-aware manufacturing test.

[BibT_eX]

[DOI]

Urban Ingelsson

Proceedings of the 2011 IEEE International Test Conference, 2011

Simplified logic design methodology for fuzzy membership function based robust detection of maternal modulus maxima location: A low complexity Fetal ECG extraction architecture for mobile health monitoring systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Improved DFT for Testing Power Switches.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

Ultra low-power photovoltaic MPPT technique for indoor and outdoor wireless sensor nodes.

[BibT_eX]

[DOI]

Alex S. Weddell

Geoff V. Merrett

Proceedings of the Design, Automation and Test in Europe, 2011

Accelerated simulation of tunable vibration energy harvesting systems using a linearised state-space technique.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Sub-clock power-gating technique for minimising leakage power during active mode.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs.

[BibT_eX]

[DOI]

Yi Zhao

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks.

[BibT_eX]

[DOI]

Luca Benini

IEEE Trans. Very Large Scale Integr. Syst., 2010

An Energy-Efficient Error Correction Scheme for IEEE 802.15.4 Wireless Sensor Networks.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Gate-Sizing-Based Single V<sub>dd</sub> Test for Bridge Defects in Multivoltage Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Fault-tolerance techniques for hybrid CMOS/nanoarchitecture.

[BibT_eX]

[DOI]

Aissa Melouki

Saket Srivastava

IET Comput. Digit. Tech., 2010

Design of Fixed-Point Processing Based Turbo Codes Using Extrinsic Information Transfer Charts.

[BibT_eX]

[DOI]

Proceedings of the 72nd IEEE Vehicular Technology Conference, 2010

Modeling the impact of process variation on resistive bridge defects.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Scan based methodology for reliable state retention power gating designs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Soft error-aware design optimization of low power and time-constrained embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Evaluation and design exploration of solar harvested-energy prediction algorithm.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Diagnosis of Multiple-Voltage Design With Bridge Defect.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Process Variation-Aware Test for Resistive Bridges.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip.

[BibT_eX]

[DOI]

J. Low Power Electron., 2009

Defect-tolerant n<sup>2</sup>-transistor structure for reliable nanoelectronic designs.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2009

Hardware reduction methodology for 2-dimensional kurtotic fastica based on algorithmic analysis and architectural symmetry.

[BibT_eX]

[DOI]

Amit Acharyya

Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Energy-Aware Simulation for Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the Sixth Annual IEEE Communications Society Conference on Sensor, 2009

Design of a low power MPEG-1 motion vector reconstructor.

[BibT_eX]

[DOI]

M. A. Ochoa-Montiel

Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism.

[BibT_eX]

[DOI]

Saket Srivastava

Aissa Melouki

Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

HSPICE implementation of a numerically efficient model of CNT transistor.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2009

Hardware efficient fixed-point VLSI architecture for 2D Kurtotic FastICA.

[BibT_eX]

[DOI]

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

An automated design flow for vibration-based energy harvester systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Variation resilient adaptive controller for subthreshold circuits.

[BibT_eX]

[DOI]

Biswajit Mishra

Proceedings of the Design, Automation and Test in Europe, 2009

Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Selective state retention design using symbolic simulation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008

Bridging Fault Test Method With Adaptive Power Management Awareness.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

Subthreshold FIR Filter Architecture for Ultra Low Power Applications.

[BibT_eX]

[DOI]

Biswajit Mishra

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Reduced Z-datapath Cordic Rotator.

[BibT_eX]

[DOI]

Karim El-Shabrawy

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A New Approach for Transient Fault Injection Using Symbolic Simulation.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

An Empirical Energy Model for Supercapacitor Powered Wireless Sensor Nodes.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Computer Communications and Networks, 2008

A Structured Hardware/Software Architecture for Embedded Sensor Nodes.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Computer Communications and Networks, 2008

Iterative Decoding for Redistributing Energy Consumption in Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Computer Communications and Networks, 2008

VHDL-AMS Implementation of a Numerical Ballistic CNT Model.

[BibT_eX]

[DOI]

Proceedings of the Languages for Embedded Systems and their Applications, 2008

VHDL-AMS Implementation of a Numerical Ballistic CNT Model for Logic Circuit Simulation.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2008

Advancement in color image processing using Geometric Algebra.

[BibT_eX]

[DOI]

Biswajit Mishra

Peter R. Wilson

Proceedings of the 2008 16th European Signal Processing Conference, 2008

Bridge Defect Diagnosis for Multiple-Voltage Design.

[BibT_eX]

[DOI]

Proceedings of the 13th European Test Symposium, 2008

MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Integrated approach to energy harvester mixed technology modelling and performance optimisation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Serialized Asynchronous Links for NoC.

[BibT_eX]

[DOI]

Crescenzo D'Alessandro

Luca Benini

Proceedings of the Design, Automation and Test in Europe, 2008

Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Asynchronous transient resilient links for NoC.

[BibT_eX]

[DOI]

Simon Ogg

Alexandre Yakovlev

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

The Superchip: Innovative teaching of IC design and manufacture.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Hardware Dependability in the Presence of Soft Errors.

[BibT_eX]

[DOI]

Ashish Darbari

Proceedings of the Visions of Computer Science, 2008

Variation Aware Analysis of Bridging Fault Testing.

[BibT_eX]

[DOI]

Urban Ingelsson

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Hardware development for pervasive healthcare systems: Current status and future directions.

[BibT_eX]

[DOI]

Amit Acharyya

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Transistor-level based defect tolerance for reliable nanoelectronics.

[BibT_eX]

[DOI]

Aiman H. El-Maleh

Aissa Melouki

Proceedings of the 6th ACS/IEEE International Conference on Computer Systems and Applications, 2008

2007

Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

Enhancing delay fault coverage through low-power segmented scan.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

Reducing Interconnect Cost in NoC through Serialized Asynchronous Links.

[BibT_eX]

[DOI]

Simon Ogg

Enrico Valli

Crescenzo D'Alessandro

Alexandre Yakovlev

Luca Benini

Proceedings of the First International Symposium on Networks-on-Chips, 2007

A fast, numerical circuit-level model of carbon nanotube transistor.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint.

[BibT_eX]

[DOI]

Yuan Cai

Sudhakar M. Reddy

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Architecture Level Power-Performance Tradeoffs for Pipelined Designs.

[BibT_eX]

[DOI]

Haider Ali

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Testing of Level Shifters in Multiple Voltage Designs.

[BibT_eX]

[DOI]

Noohul Basheer Zain Ali

Proceedings of the 14th IEEE International Conference on Electronics, 2007

March CRF: an Efficient Test for Complex Read Faults in SRAM Memories.

[BibT_eX]

[DOI]

Luigi Dilillo

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Resistive Bridging Faults DFT with Adaptive Power Management Awareness.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection.

[BibT_eX]

[DOI]

M. A. Ochoa-Montiel

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Dual Flow Nets: Modeling the control/data-flow relation in embedded systems.

[BibT_eX]

[DOI]

Mauricio Varea

Luis Alejandro Cortés

Zebo Peng

ACM Trans. Embed. Comput. Syst., 2006

Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Reducing Power Dissipation in SRAM during Test.

[BibT_eX]

[DOI]

J. Low Power Electron., 2006

New JETTA Editors, 2006.

[BibT_eX]

[DOI]

J. Electron. Test., 2006

Conference Reports.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2006

Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal.

[BibT_eX]

[DOI]

Simon Ogg

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

On-Chip Time Measurement Architecture with Femtosecond Timing Resolution.

[BibT_eX]

[DOI]

Matthew Collins

Proceedings of the 11th European Test Symposium, 2006

Dynamic Voltage Scaling Aware Delay Fault Testing.

[BibT_eX]

[DOI]

Noohul Basheer Zain Ali

Proceedings of the 11th European Test Symposium, 2006

Minimizing test power in SRAM through reduction of pre-charge activity.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Improving routing efficiency for network-on-chip through contention-aware input selection.

[BibT_eX]

[DOI]

Dong Wu

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Cache size selection for performance, energy and reliability of time-constrained systems.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Synchronization overhead in SOC compressed test.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Application of analog adaptive filters for dynamic sensor compensation.

[BibT_eX]

[DOI]

Mehdi Jafaripanah

Neil M. White

IEEE Trans. Instrum. Meas., 2005

Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

A novel switched-current phase locked loop.

[BibT_eX]

[DOI]

Peter R. Wilson

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis.

[BibT_eX]

[DOI]

M. A. Ochoa-Montiel

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Adaptive sensor response correction using analog filter compatible with digital technology [load cell sensor applications].

[BibT_eX]

[DOI]

Mehdi Jafaripanah

Neil M. White

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Battery-aware dynamic voltage scaling in multiprocessor embedded system.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A programmable time measurement architecture for embedded memory characterization.

[BibT_eX]

[DOI]

Matthew Collins

J. Neil Ross

Proceedings of the 10th European Test Symposium, 2005

Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction.

[BibT_eX]

[DOI]

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling.

[BibT_eX]

[DOI]

Enkelejda Tafaj

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Rapid Generation of Thermal-Safe Test Schedules.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

Iterative schedule optimization for voltage scalable distributed embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2004

New high-order filter structures using only single-ended-input OTAs and grounded capacitors.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2004

Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Testability Trade-Offs for BIST Data Paths.

[BibT_eX]

[DOI]

J. Electron. Test., 2004

Leakage Power Analysis and Comparison of Deep Submicron Logic Gates.

[BibT_eX]

[DOI]

Geoff V. Merrett

Proceedings of the Integrated Circuit and System Design, 2004

Analogue adaptive filters using wave synthesis technique.

[BibT_eX]

[DOI]

Yan Xie

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Power-conscious design methodology for class-A switched-current wave filters.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A compression-driven test access mechanism design approach.

[BibT_eX]

[DOI]

Proceedings of the 9th European Test Symposium, 2004

Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique.

[BibT_eX]

[DOI]

Matheos Lampropoulos

Proceedings of the 2004 Design, 2004

Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

System-level design techniques for energy-efficient embedded systems.

[BibT_eX]

[DOI]

Springer, ISBN: 978-1-4020-7750-0, 2004

2003

Addressing useless test data in core-based system-on-a-chip test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Variable-length input Huffman coding for system-on-a-chip test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Power-Conscious Test Synthesis and Scheduling.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

Load cell response correction using analog adaptive techniques.

[BibT_eX]

[DOI]

Mehdi Jafaripanah

Neil M. White

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Analytical synthesis of voltage mode OTA-C all-pass filters for high frequency operation.

[BibT_eX]

[DOI]

Chun-Ming Chang

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A CAD methodology for switched current analog IP cores.

[BibT_eX]

[DOI]

Proceedings of 9th IEEE International Conference on Emerging Technologies and Factory Automation, 2003

Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems.

[BibT_eX]

[DOI]

Dong Wu

Proceedings of the 2003 Design, 2003

A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric.

[BibT_eX]

[DOI]

Petros Oikonomakos

Proceedings of the 2003 Design, 2003

Test Data Compression: The System Integrator's Perspective.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

Power profile manipulation: a new approach for reducing test application time under power constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2002

Synthesizing Energy-Efficient Embedded Systems with LOPOCOS.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2002

Guest Editor Introduction.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2002

Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Application of group delay equalisation in testing fully-balanced OTA-C filters.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Scan Architecture for Shift and Capture Cycle Power Reduction.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Symbolic model checking of Dual Transition Petri Nets.

[BibT_eX]

[DOI]

Mauricio Varea

Luis Alejandro Cortés

Zebo Peng

Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001

Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Considering power variations of DVS processing elements for energy minimisation in distributed systems.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Power constrained test scheduling using power profile manipulation.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Dual transitions petri net based modelling technique for embedded systems specification.

[BibT_eX]

[DOI]

Mauricio Varea

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Testability trade-offs for BIST RTL data paths: the case for three dimensional design space.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

BIST hardware synthesis for RTL data paths based on testcompatibility classes.

[BibT_eX]

[DOI]

Alan Christopher Williams

Andrew D. Brown

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Power conscious test synthesis and scheduling for BIST RTL data paths.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

1999

New differential coefficient coding algorithm for recursive FIR filters.

[BibT_eX]

[DOI]

J. Living

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Mixed arithmetic architecture: a solution to the iteration bound for resource efficient FPGA and CPLD recursive digital filters.

[BibT_eX]

[DOI]

J. Living

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Compensation of nonideal effects in video-frequency sinc(x)-equalizers using tunable gm-C structure.

[BibT_eX]

[DOI]

F. Dudek

M. Moniri

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

Correction to the Proof of Theorem 2 in "Parallel Signature Analysis Design with Bounds on Aliasing".

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1998

High performance distributed arithmetic FPGA decimators for video-frequency applications.

[BibT_eX]

[DOI]

Jonathan Living