Basavaraj Talawar
Orcid: 0000-0001-5054-3124Affiliations:
- National Institute of Technology Karnataka, Surathkal, India
According to our database1,
Basavaraj Talawar
authored at least 36 papers
between 2007 and 2024.
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Bibliography
2024
A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment.
IEEE Access, 2024
2022
LBF-NoC: Learning-Based Framework to Predict Performance, Power and Area for Network-On-Chip Architectures.
J. Circuits Syst. Comput., 2022
Knowledgeable network-on-chip accelerator for fast and accurate simulations using supervised learning algorithms and multiprocessing.
Int. J. Intell. Eng. Informatics, 2022
Decentralised priority-based shortest job first queue model for IoT gateways in fog computing.
Int. J. Grid Util. Comput., 2022
2021
Computing, 2021
Parallel Version of Local Search Heuristic Algorithm to Solve Capacitated Vehicle Routing Problem.
Clust. Comput., 2021
Clust. Comput., 2021
2020
P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA.
Wirel. Pers. Commun., 2020
LBNoC: Design of Low-latency Router Architecture with Lookahead Bypass for Network-on-Chip Using FPGA.
ACM Trans. Design Autom. Electr. Syst., 2020
ELBA-NoC: ensemble learning-based accelerator for 2D and 3D network-on-chip architectures.
Int. J. Comput. Sci. Eng., 2020
An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks.
Circuits Syst. Signal Process., 2020
Comput. Electr. Eng., 2020
Proceedings of the 2020 IEEE Conference on Network Function Virtualization and Software Defined Networks, 2020
2019
Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures.
Simul. Model. Pract. Theory, 2019
Analysis of cache behaviour and software optimizations for faster on-chip network simulations.
Int. J. Syst. Assur. Eng. Manag., 2019
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs.
J. Circuits Syst. Comput., 2019
Concurr. Comput. Pract. Exp., 2019
High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the 10th International Conference on Computing, 2019
2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Floorplan Based Performance Evaluation of 3D Variants of Mesh and BFT Networks-on-Chip.
Proceedings of the 2018 International Conference on Signal Processing and Communications (SPCOM), 2018
Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018
Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018
Proceedings of the Intelligent Systems Design and Applications, 2018
Proceedings of the 2018 International Conference on Advances in Computing, 2018
Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks.
Proceedings of the 2018 Eleventh International Conference on Contemporary Computing, 2018
2017
GPU implementation of non-local maximum likelihood estimation method for denoising magnetic resonance images.
J. Real Time Image Process., 2017
GPU-Based Iterative Hill Climbing Algorithm to Solve Symmetric Traveling Salesman Problem.
Proceedings of the Big Data and HPC: Ecosystem and Convergence, TopHPC 2017, 2017
2016
Proceedings of the 11th International Conference on Industrial and Information Systems, 2016
2015
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015
2013
2009
Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
2007