Basant K. Mohanty
Orcid: 0000-0002-1542-1575
According to our database1,
Basant K. Mohanty
authored at least 49 papers
between 2006 and 2024.
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Bibliography
2024
Memory-Efficient Multiplier-Less 2-D DWT Design Using Combined Convolution and Lifting Schemes for Wireless Visual Sensors.
IEEE Trans. Very Large Scale Integr. Syst., April, 2024
2023
A novel computing scheme based on pattern matching for identification of nephron loss and chronic kidney disease stage.
Turkish J. Electr. Eng. Comput. Sci., November, 2023
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
2021
Chronic kidney disease stage identification using texture analysis of ultrasound images.
Biomed. Signal Process. Control., 2021
2020
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Parallel VLSI Architecture for Approximate Computation of Discrete Hadamard Transform.
IEEE Trans. Circuits Syst. Video Technol., 2020
J. Circuits Syst. Comput., 2020
2019
Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
2018
Hardware Design for VLSI Implementation of Acoustic Feedback Canceller in Hearing Aids.
Circuits Syst. Signal Process., 2018
Novel Data-Access Scheme and Efficient Parallel Architecture for Multi-level Lifting 2-D DWT.
Circuits Syst. Signal Process., 2018
2017
Hardware Design for VLSI Implementation of FxLMS- and FsLMS-Based Active Noise Controllers.
Circuits Syst. Signal Process., 2017
Efficient Design for Radix-8 Booth Multiplier and Its Application in Lifting 2-D DWT.
Circuits Syst. Signal Process., 2017
2016
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter.
IEEE Trans. Very Large Scale Integr. Syst., 2016
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic.
J. Circuits Syst. Comput., 2016
A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic.
Integr., 2016
Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer.
Circuits Syst. Signal Process., 2016
2015
FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Efficient very large-scale integration architecture for variable length block least mean square adaptive filter.
IET Signal Process., 2015
Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters.
Proceedings of the 28th International Conference on VLSI Design, 2015
Critical-path optimization for efficient hardware realization of lifting and flipping DWTs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
FPGA implementation of LMS-based FIR adaptive filter for real time digital signal processing applications.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Leakage-aware intra-task dynamic voltage scaling technique for energy reduction in real-time embedded systems.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
2014
IEEE Trans. Circuits Syst. Video Technol., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation.
IET Image Process., 2014
Circuits Syst. Signal Process., 2014
Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm.
IEEE Trans. Signal Process., 2013
Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT.
IEEE Trans. Circuits Syst. Video Technol., 2013
J. Low Power Electron., 2013
Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-buffer.
IET Circuits Devices Syst., 2013
Systolic architecture for hardware implementation of two-dimensional non-separable filter-bank.
Proceedings of the 8th International Design and Test Symposium, 2013
2012
Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Signal Process., 2011
Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT.
IEEE Trans. Signal Process., 2011
2010
Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT.
IEEE Trans. Circuits Syst. Video Technol., 2010
Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2008
Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
2006
Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006