Bart Vermeulen

According to our database, Bart Vermeulen authored at least 49 papers between 1999 and 2021.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2021

Automotive Architecture Topologies: Analysis for Safety-Critical Autonomous Vehicle Applications.

Alessandro Frigerio, Bart Vermeulen, Kees G. W. Goossens

IEEE Access, 2021

Isolation of redundant and mixed-critical automotive applications: effects on the system architecture.

Alessandro Frigerio, Bart Vermeulen, Kees Goossens

Proceedings of the 93rd IEEE Vehicular Technology Conference, 2021

2020

A Distributed Safety Mechanism using Middleware and Hypervisors for Autonomous Vehicles.

Tjerk Bijlsma, Andrii Buriachevskyi, Alessandro Frigerio, Yuting Fu, Kees Goossens, Ali Osman Örs, Pieter J. van der Perk, Andrei Sergeevich Terechko, Bart Vermeulen

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Component-Level ASIL Decomposition for Automotive Architectures.

Alessandro Frigerio, Bart Vermeulen, Kees Goossens

Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2019

2018

A Generic Method for a Bottom-Up ASIL Decomposition.

Alessandro Frigerio, Bart Vermeulen, Kees Goossens

Proceedings of the Computer Safety, Reliability, and Security, 2018

2016

Overview of Health Monitoring Techniques for Reliability.

Abhijit K. Deb, Bart Vermeulen, Luc van Dijk

Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

2014

Transient errors resiliency analysis technique for automotive safety critical applications.

Sujan Pandey, Bart Vermeulen

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Startup error detection and containment to improve the robustness of hybrid FlexRay networks.

Alexander Kordes, Bart Vermeulen, Abhijit K. Deb, Michael G. Wahl

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2012

Architecture and design flow for a debug event distribution interconnect.

Arnaldo Azevedo, Bart Vermeulen, Kees Goossens

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011

Interactive Debug of SoCs with Multiple Clocks.

Bart Vermeulen, Kees Goossens

IEEE Des. Test Comput., 2011

Optimal scheduling of switched FlexRay networks.

Thijs Schenkelaars, Bart Vermeulen, Kees Goossens

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Webcams for Bird Detection and Monitoring: A Demonstration Study.

Willem W. Verstraeten, Bart Vermeulen, Jan Stuckens, Stefaan Lhermitte, Dimitry Van der Zande, Marc Van Ranst, Pol Coppin

Sensors, 2010

Obtaining more information from conjoint experiments by best-worst choices.

Bart Vermeulen, Peter Goos, Martina Vandebroek

Comput. Stat. Data Anal., 2010

INDEXYS, a Logical Step beyond GENESYS.

Andreas Eckel, Paul Milbredt, Zaid Al-Ars, Stefan Schneele, Bart Vermeulen, György Csertán, Christoph Scheerer, Neeraj Suri, Abdelmajid Khelil, Gerhard Fohler

Proceedings of the Computer Safety, 2010

On-line dependability enhancement of multiprocessor SoCs by resource management.

Timon D. ter Braak, S. T. Burgess, H. Hurskainen, Hans G. Kerkhoff, Bart Vermeulen, Xiao Zhang

Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks.

Bart Vermeulen, Kees Goossens

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism.

Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen

Proceedings of the 15th European Test Symposium, 2010

A distributed architecture to check global properties for post-silicon debug.

Erik Larsson, Bart Vermeulen, Kees Goossens

Proceedings of the 15th European Test Symposium, 2010

Switched FlexRay: Increasing the effective bandwidth and safety of FlexRay networks.

Paul Milbredt, Bart Vermeulen, Gökhan Tabanoglu, Martin Lukasiewycz

Proceedings of 15th IEEE International Conference on Emerging Technologies and Factory Automation, 2010

On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism.

Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

A high-level debug environment for communication-centric debug.

Kees Goossens, Bart Vermeulen, Ashkan Beyranvand Nejad

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis.

Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat, Paul Wielage, Sebastien Mouy, Bart Vermeulen, Marc J. M. Heijligers

IEEE J. Solid State Circuits, 2008

Overview of Debug Standardization Activities.

Bart Vermeulen, Neal Stollon, Rolf Kühnis, Gary Swoboda, Jeff Rearick

IEEE Des. Test Comput., 2008

Functional Debug Techniques for Embedded Systems.

Bart Vermeulen

IEEE Des. Test Comput., 2008

Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip.

Bart Vermeulen, Kees Goossens, Siddharth Umrani

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Integration of Hardware Assertions in Systems-on-Chip.

Jeroen Geuzebroek, Bart Vermeulen

Proceedings of the 2008 IEEE International Test Conference, 2008

You can catch more bugs with transaction level honey.

Miron Abramovici, Kees Goossens, Bart Vermeulen, Jack Greenbaum, Neal Stollon, Adam Donlin

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007

Debug architecture for the En-II system chip.

Bart Vermeulen, Sjaak Bakker

IET Comput. Digit. Tech., 2007

Transaction-Based Communication-Centric Debug.

Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Communication-Centric SoC Debug Using Transactions.

Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek

Proceedings of the 12th European Test Symposium, 2007

A Run-Time Memory Protection Methodology.

Udaya Seshua, Nagaraju Bussa, Bart Vermeulen

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2005

Optimal Interconnect ATPG Under a Ground-Bounce Constraint.

Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen

J. Electron. Test., 2005

Test and debug features of the RTO7 chip.

Kees van Kaam, Bart Vermeulen, Henk Jan Bergveld

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

Trends in Testing Integrated Circuits.

Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Automatic generation of breakpoint hardware for silicon debug.

Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel

Proceedings of the 41th Design Automation Conference, 2004

2003

Multi-TAP Controller Architecture for Digital System Chips.

Bart Vermeulen, Tom Waayers, Sjaak Bakker

J. Electron. Test., 2003

Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.

Sandeep Kumar Goel, Bart Vermeulen

J. Electron. Test., 2003

Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint.

Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts

IEEE Des. Test Comput., 2003

Bringing communication networks on a chip: test and verification implications.

Bart Vermeulen, John Dielissen, Kees Goossens, Calin Ciordas

IEEE Commun. Mag., 2003

Creating Value Through Test.

Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller

Proceedings of the 2003 Design, 2003

2002

Design for Debug: Catching Design Errors in Digital Chips.

Bart Vermeulen, Sandeep Kumar Goel

IEEE Des. Test Comput., 2002

Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer?

Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Core-Based Scan Architecture for Silicon Debug.

Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips.

Bart Vermeulen, Tom Waayers, Sjaak Bakker

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

TAPS All Over My Chips! So Now What Do I Do?

Bart Vermeulen

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.

Sandeep Kumar Goel, Bart Vermeulen

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Test and debug strategy of the PNX8525 Nexperia^TM digital video platform system chip.

Bart Vermeulen, Steven Oostdijk, Frank Bouwman

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

Silicon debug of a co-processor array for video applications.

Bart Vermeulen, Gert-Jan van Rootselaar

Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

1999

Silicon debug: scan chains alone are not enough.

Gert-Jan van Rootselaar, Bart Vermeulen

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999