Barry Daly
According to our database1,
Barry Daly
authored at least 12 papers
between 2006 and 2015.
Collaborative distances:
Collaborative distances:
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Bibliography
2015
IEEE J. Solid State Circuits, 2015
2014
IEEE J. Solid State Circuits, 2014
A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems.
IEEE J. Solid State Circuits, 2014
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
Proceedings of the Symposium on VLSI Circuits, 2014
2013
A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
IEEE J. Solid State Circuits, 2011
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2007
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
Use of a Thin-Section Archive and Enterprise 3D Software for Long-Term Storage of Thin-Slice CT Data Sets.
J. Digit. Imaging, 2006
Proceedings of the Medical Imaging 2006: Image Processing, 2006