Baris Taskin

IEEE Micro, 2022

Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 0.45 pJ/bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Scalable Resonant Power Clock Generation for Adiabatic Logic Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020

TSV Antennas for Multi-Band Wireless Communication.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

FinFET - Based Low Swing Rotary Traveling Wave Oscillators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

SnackNoC: Processing in the Communication Layer.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019

SLECTS: Slew-Driven Clock Tree Synthesis.

[BibT_eX]

[DOI]

Savithri Sundareswaran

Benjamin Huang

IEEE Trans. Very Large Scale Integr. Syst., 2019

Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors.

[BibT_eX]

[DOI]

Isikcan Yilmaz

IEEE Trans. Very Large Scale Integr. Syst., 2019

Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

FOPAC: Flexible On-Chip Power and Clock.

[BibT_eX]

[DOI]

Selçuk Köse

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

The Adiabatically Driven StrongARM Comparator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM/IEEE International Workshop on System Level Interconnect Prediction, 2019

3D NoCs with active interposer for multi-die systems.

[BibT_eX]

[DOI]

Vasil Pano

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

On-chip wireless interconnect paradigm.

[BibT_eX]

[DOI]

Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

Robust Low Power Clock Synchronization for Multi-Die Systems.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Low Swing - Low Frequency Rotary Traveling Wave Oscillators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Low Voltage Clock Tree Synthesis with Local Gate Clusters.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018

Vertical Arbitration-Free 3-D NoCs.

[BibT_eX]

[DOI]

Vasil Pano

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

SynchroTrace: Synchronization-Aware Architecture-Agnostic Traces for Lightweight Multicore Simulation of CMP and HPC Workloads.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2018

Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

NoC Router Lifetime Improvement using Per-Port Router Utilization.

[BibT_eX]

[DOI]

Vasil Pano

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Low Frequency Rotary Traveling Wave Oscillators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 900 MHz Charge Recovery Comparator With 40 fJ per Conversion.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

2017

Special issue on IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016.

[BibT_eX]

[DOI]

Tsung-Yi Ho

Integr., 2017

Slew-down: analysis of slew relaxation for low-impact clock buffers.

[BibT_eX]

[DOI]

Eric Leggett

Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

A charge recovery logic system bus.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

Charge recovery implementation of an analog comparator: Initial results.

[BibT_eX]

[DOI]

Lunal Khuon

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Wireless NoCs Using Directional and Substrate Propagation Antennas.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Wireless charge recovery system for implanted electroencephalography applications in mice.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Stability of Rotary Traveling Wave Oscillators under process variations and NBTI.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Reconfigurable threshold logic gates using optoelectronic capacitors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Design Methodology for Voltage-Scaled Clock Distribution Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Exploiting useful skew in gated low voltage clock trees.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Charge recovery logic for thermal harvesting applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Energy aware routing of multi-level Network-on-Chip traffic.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Wireless Network-on-Chip analysis of propagation technique for on-chip communication.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015

ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Locality-Aware Network Utilization Balancing in NoCs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

FinFET-Based Low-Swing Clocking.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2015

Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

Synchrotrace: synchronization-aware architecture-agnostic traces for light-weight multicore simulation.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Enhanced level shifter for multi-voltage operation.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A wirelessly powered system with charge recovery logic.

[BibT_eX]

[DOI]

Emre Salman

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling.

[BibT_eX]

[DOI]

Karthik Sangaiah

Mark Hempstead

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A Novel Static D-Flip-Flop Topology for Low Swing Clocking.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Iterative skew minimization for low swing clocks.

[BibT_eX]

[DOI]

Integr., 2014

Range-based dynamic routing of hierarchical on chip network traffic.

[BibT_eX]

[DOI]

Julian Kemmerer

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Timing characterization of clock buffers for clock tree synthesis.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Static thread mapping for NoCs via binary instrumentation traces.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Frequency-centric resonant rotary clock distribution network design.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013

Wireless on Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

A microcontroller-based embedded system design course with PSoC3.

[BibT_eX]

[DOI]

Prawat Nagvajara

Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Resonant frequency divider design methodology for dynamic frequency scaling.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Rotary traveling wave oscillator frequency division at nanoscale technologies.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Multi-corner multi-voltage domain clock mesh design.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Skew-bounded low swing clock tree optimization.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Sparse-rotary oscillator array (SROA) design for power and skew reduction.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

ZeROA: Zero Clock Skew Rotary Oscillatory Array.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Integrated Clock Mesh Synthesis With Incremental Register Placement.

[BibT_eX]

[DOI]

Xiaomi Mao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

3-D Parasitic Modeling for Rotary Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on VLSI Design, 2012

A locality-aware bi-level mesh-mesh 2d-noc architecture for future thousand core CMPs.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on System Level Interconnect Prediction, 2012

A unified design methodology for a hybrid wireless 2-D NoC.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Clock mesh synthesis method using the Earth Mover's Distance under transformations.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Multi-voltage domain clock mesh design.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Clock mesh synthesis with gated local trees and activity driven register clustering.

[BibT_eX]

[DOI]

Xiaomi Mao

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

High-Performance, Low-Power Resonant Clocking: Embedded tutorial.

[BibT_eX]

[DOI]

Matthew R. Guthaus

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Synchronization scheme for brick-based rotary oscillator arrays.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011

CROA: Design and Analysis of the Custom Rotary Oscillatory Array.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Clock buffer polarity assignment with skew tuning.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2011

Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling.

[BibT_eX]

[DOI]

Shannon M. Kurtas

J. Circuits Syst. Comput., 2011

Simulation based study of on-chip antennas for a reconfigurable hybrid 2D wireless network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

From RTL to GDSII: An ASIC design course development using Synopsys® University Program.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

Process variation sensitivity of the Rotary Traveling Wave Oscillator.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis.

[BibT_eX]

[DOI]

Xiaomi Mao

Proceedings of the 2011 International Symposium on Physical Design, 2011

Reconfigurable clock polarity assignment for peak current reduction of clock-gated circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

[BibT_eX]

[DOI]

Yusuf Aksehir

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

ROA-brick topology for rotary resonant clocks.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Steiner tree based rotary clock routing with bounded skew and capacitive load balancing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Post-CTS Delay Insertion.

[BibT_eX]

[DOI]

VLSI Design, 2010

Look-Up Table Based Low Power Rotary Traveling Wave Oscillator Design Considering the Skin Effect.

[BibT_eX]

[DOI]

J. Low Power Electron., 2010

Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Simulation based study of wireless RF interconnects for practical CMOs implementation.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Clock Tree Synthesis with XOR Gates for Polarity Assignment.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Leakage current analysis for intra-chip wireless interconnects.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Clock buffer polarity assignment considering capacitive load.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Skew analysis and bounded skew constraint methodology for rotary clocking technology.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

PEEC based parasitic modeling for power analysis on custom rotary rings.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnects.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

Custom topology rotary clock router with tree subnetworks.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

A shift-register-based QCA memory architecture.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2009

Multi-Phase Rotary Clock Synchronization of Level-Sensitive Circuits.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2009

Zero clock skew synchronization with rotary clocking technology.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking.

[BibT_eX]

[DOI]

Bo Hong

IEEE Trans. Very Large Scale Integr. Syst., 2008

Custom rotary clock router.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

2007

Design-for-Debug: A Vital Aspect in Education.

[BibT_eX]

[DOI]

Prawat Nagvajara

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

2006

Delay Insertion Method in Clock Skew Scheduling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2004

Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Performance improvement of edge-triggered sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Advanced timing of level-sensitive sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2002

Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew.

[BibT_eX]

[DOI]