Bapi Kar

Pradeep Kumar Gopalakrishnan

Mohendra Roy

Arindam Basu

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

A Stacked Autoencoder Neural Network based Automated Feature Extraction Method for Anomaly detection in On-line Condition Monitoring.

[BibT_eX]

[DOI]

Mohendra Roy

Sumon Kumar Bose

Pradeep Kumar Gopalakrishnan

Arindam Basu

Proceedings of the IEEE Symposium Series on Computational Intelligence, 2018

2016

A Novel EPE Aware Hybrid Global Route Planner after Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

An early global routing framework for uniform wire distribution in SoCs.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2015

A New Method for Defining Monotone Staircases in VLSI Floorplans.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014

Global Routing Using Monotone Staircases with Minimal Bends.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A novel architecture for QPSK modulation based on time-mode signal processing.

[BibT_eX]

[DOI]

Sumit Saha

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2013

STAIRoute: Global routing using monotone staircase channels.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2012

A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts.

[BibT_eX]

[DOI]

Sridhar H. Rangarajan