Baoyu Xiong

According to our database, Baoyu Xiong authored at least 5 papers between 2011 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power.

Fujun Bai, Baoyu Xiong, Xiaofei Xue, Weizhe Song, Baofeng Wu, Ni Fu, Bing Yu, Huifu Duan, Xiaowei Han, Alessandro Minzoni, Qiwei Ren

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2012

Design of a high information-density multiple valued 2-read 1-write register file.

Yuejun Zhang, Pengjun Wang, Baoyu Xiong, Zhiyi Yu

IEICE Electron. Express, 2012

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS.

Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng

IEICE Electron. Express, 2012

2011

Design of a single-ended cell based 65nm 32×32b 4R2W register file.

Baoyu Xiong, Xingxing Zhang, Jun Han, Zhiyi Yu, Xiaoyang Zeng

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A control scheme for a 65nm 32×32b 4-read 2-write register file.

Jun Han, Xingxing Zhang, Baoyu Xiong, Zhiyi Yu, Xiaoyang Zeng

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011