Baoyong Chi
Orcid: 0000-0003-4399-4423
According to our database1,
Baoyong Chi
authored at least 171 papers
between 2003 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, October, 2024
IEEE J. Solid State Circuits, October, 2024
A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces.
IEEE J. Solid State Circuits, October, 2024
28 GHz Compact LNAs With 1.9 dB Minimum NF Using Folded Three-Coil Transformer and Dual-Feedforward Techniques for Phased Array Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024
An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique.
IEEE J. Solid State Circuits, August, 2024
IEEE J. Solid State Circuits, July, 2024
Correction to "A 4.4-GHz 193.2-dB FoM 8-Shaped-Inductor-Based LC-VCO Using Orthogonal-Coupled Triple-Coil Transformer".
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024
A Band-Shifting Millimeter-Wave T/R Front-End Using Inductance-Mutation Transformer Technique for Multiband Phased-Array Transceivers.
IEEE J. Solid State Circuits, May, 2024
A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer.
IEEE J. Solid State Circuits, January, 2024
A 132-to-163 GHz 4TX/4RX Distributed MIMO FMCW Radar Transceiver with Real-Time Reference-Clock Synchronization Enabling Cooperative Coherent Multistatic Imaging System.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
19.5 A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 24.3-to-44.8 GHz Reconfigurable Dual-Band T/R Front-End with An Implicit Switch-based Antenna Interface Supporting 600MSym/s 64QAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3f5 Jitter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 194.9dBc/Hz FoM and 6.8-to-11.6GHz Quad-Core Dual-Mode Class-F VCO Featuring Wideband Flicker Noise Suppression.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 24-30-GHz Four-Element Phased Array Transceiver With Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter for 5G Communication.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023
A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique.
IEEE J. Solid State Circuits, October, 2023
A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS.
IEEE J. Solid State Circuits, February, 2023
IEEE J. Solid State Circuits, February, 2023
An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1<sup>st</sup>/2<sup>nd</sup>-Order DTC INL Calibration.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 6.5-to-8GHz IEEE 802.15.4z-compliant All-Digital UWB Transmitter with Integrated Fast-Settling Master-Slave Regulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
INVITED PAPER: A 312.5Mbps-32Gbps JESD204C Wireline Transceiver Back-Compatible with JESD204B in 28nm CMOS.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 37-to-41.8 GHz Double-Gm-Boosting LNA with 2.9-dB NFmin Using Quadruple-Coupling Transformer for Phased-Array Transceivers.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 25.0-to-35.9GHz Dual-Layer Quad-Core Dual-Mode VCO with 189.1dBc/Hz FoM and 200.2dBc/Hz FoMT at 1MHz Offset in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A Transient Enhancement Digital LDO with Adaptive Ripple Cancelation Based on Optimal Compensation Period Approximation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A 27-to-31.6 GHz 8-Element Phased-Array Transmitter Front-End with Inter-Element-Interference Cancellation Scheme in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A Compact E-Band Load-Modulation Balanced Power Amplifier Using Coupled Transmission-Line Output Network Achieving 22.1-dBm Psat and 34.9%/12.2% Efficiency at Psat/6-dB PBO.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 4.4-GHz 193.2-dB FoM 8-Shaped-Inductor Based LC-VCO Using Orthogonal-Coupled Triple-Coil Transformer.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation.
IEEE J. Solid State Circuits, 2022
Sci. China Inf. Sci., 2022
A 53.6-to-60.2GHz Many-Core Fundamental Oscillator With Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Highly Linearized Ka-band Heterodyne Receiver using a Folded Class-AB Inductive Peaking Mixer and Magnetic-Self-Cancellation-Transformer-Based IF Amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A 22.8 GHz to 32.8 GHz Compact Power Amplifier with a 15 dBm Output P1dB and 36.5% Peak PAE in 65-nm CMOS.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logN<sub>div</sub>.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A 12.5-to-15.4GHz, -118.9dBc/Hz PN at 1MHz offset, and 191.0dBc/Hz FoM VCO with Common-Mode Resonance Expansion and Simultaneous Differential 2ND-Harmonic Output using a Single Three-Coil Transformer in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
A 76-81 GHz FMCW 2TX/3RX Radar Transceiver with Integrated Mixed-Mode PLL and Series-Fed Patch Antenna Array.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
Sci. China Inf. Sci., 2021
A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 11.1-to-14.2 GHz Self-adapted Two-point Modulation Dual-path Type-II Digital PLL Concurrently Achieving 124.7-MHz/μs Chirp Rate and 2.27-GHz Bandwidth.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 60GHz 186.5dBc/Hz FoM Quad-Core Fundamental VCO Using Circular Triple-Coupled Transformer with No Mode Ambiguity in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A C-band FMCW Radar Transmitter with a 22 dBm Output Power Series-stacking CMCD PA for Long-distance Detection in 180-nm CMOS Technology.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Optimization methods for high inductance-density inductors for high speed integrated circuits.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
A 24-30GHz 4-Element Phased Array Transceiver with Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter in 65 nm CMOS Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-bit Resolution 360° Phase Shift and 0~31.5 dB Gain Control in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A Highly Integrated Energy-efficient CMOS Millimeter-wave Transceiver with Direct-modulation Digital Transmitter, Quadrature Phased-coupled Frequency Synthesizer and Substrate-Integrated Waveguide E-shaped Patch Antenna.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC With Dual Rising-Edge Fractional-Phase Detector.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A U-Band PLL Using Implicit Distributed Resonators for Sub-THz Wireless Transceivers in 40 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Microelectron. J., 2020
A CMOS 76-81-GHz 2-TX 3-RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator.
IEEE J. Solid State Circuits, 2020
An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer.
IEEE J. Solid State Circuits, 2020
A Fully Integrated K-Band Dual Down-Conversion Receiver for Radar Applications in 90 nm CMOS.
IEEE Access, 2020
A FoM of -191 dB, 4.4-GHz LC-VCO Integrating an 8-Shaped Inductor with an Orthogonal-Coupled Tail-Filtering Inductor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 53.1-to-64.5 GHz In-Phase Coupled Quadrature Injection-Locked Oscillator with Transformer-Based I/Q-Phase Differential Injection Scheme.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
A 44-52 GHz Reflection-type Phase Shifter with 1.4° Phase Resolution in 28nm CMOS Process.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
A Highly-Integrated Ka-Band Direct Up-Conversion Transmitter for Satellite Communication in 65nm CMOS.
Proceedings of the 20th IEEE International Conference on Communication Technology, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
1.15 GHz image rejection filter with 45 dB image rejection ratio and 8.4 mW DC power in 90 nm CMOS.
Microelectron. J., 2019
A 25-35 GHz 5-bit digital attenuator with low RMS amplitude error and low phase variation in 65 nm CMOS.
IEICE Electron. Express, 2019
Circuits Syst. Signal Process., 2019
Sci. China Inf. Sci., 2019
A Wideband High PSRR Capacitor-Less LDO with Adaptive DC Level Shift and Bulk-Driven Feed-Forward Techniques in 28nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Fully Integrated 27.5-30.5 GHz 8-Element Phased-Array Transmit Front-end Module in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 0.1-5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS.
Microelectron. J., 2018
IEEE J. Solid State Circuits, 2018
A K-Band Fractional-N Frequency Synthesizer With a Low Phase Noise LC VCO in 90nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC with Dual Rising-Edge Fractional-Phase Detector.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
A CMOS 76-81 GHz 2TX 3RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
An Interference-Robust Reconfigurable Receiver With Automatic Frequency-Calibrated LNA in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A Flexible Continuous-Time Δ Σ ADC With Programmable Bandwidth Supporting Low-Pass and Complex Bandpass Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A 0.1-5.0 GHz SDR transmitter with current-mode power-mixer and self-calibration scheme in 65 nm CMOS.
Microelectron. J., 2017
A 6.6 mW 1.25-2.25 GHz low phase noise PLL frequency synthesizer based on wide tuning range Class-C VCO.
Microelectron. J., 2017
An 80-83 GHz CMOS DCO based on DiCAD technique for size, linearity and noise optimization.
Sci. China Inf. Sci., 2017
A 5-bit phase-interpolator-based fractional-N frequency divider for digital phase-locked loops.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT ΔΣ ADC With AntiPole-Splitting Opamp and Digital I/Q Calibration.
IEEE Trans. Very Large Scale Integr. Syst., 2016
A PAPR-Aware Dual-Mode Subgigahertz CMOS Power Amplifier for Short-Range Wireless Communication.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Guest Editorial for the Special Issue on Software-Defined Radio Transceivers and Circuits for 5G Wireless Communications.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Sensors, 2016
A 77 GHz Frequency Doubling Two-Path Phased-Array FMCW Transceiver for Automotive Radar.
IEEE J. Solid State Circuits, 2016
IET Circuits Devices Syst., 2016
A reconfigurable digital polar transmitter with open-loop phase modulation for Sub-GHz applications.
Proceedings of the 25th IEEE International Symposium on Industrial Electronics, 2016
A reconfigurable IF receiver supporting intra-band non-contiguous carrier aggregation in 65 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A 32.9% PAE, 15.3 dBm, 21.6-41.6 GHz power amplifier in 65nm CMOS using coupled resonators.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A 0.1-6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A 0.1-1.5 GHz Harmonic Rejection Receiver Front-End With Phase Ambiguity Correction, Vector Gain Calibration and Blocker-Resilient TIA.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A 60-GHz CMOS Dual-Mode Power Amplifier With Efficiency Enhancement at Low Output Power.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
An LP/CBP reconfigurable analog baseband circuit for software-defined radio receivers in 65 nm CMOS.
Microelectron. J., 2015
A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS.
IEEE J. Solid State Circuits, 2015
Proceedings of the VLSI Design, Automation and Test, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 0.5-30GHz wideband differential CMOS T/R switch with independent bias and leakage cancellation techniques.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Relay-Based Cooperative Spectrum Sensing with Improved Energy Detection In Cognitive Radio.
Proceedings of the 10th International Conference on Broadband and Wireless Computing, 2015
A 180nm CMOS wireless transceiver by utilizing guard band for narrowband IoT applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
A 1/2/4MHz multi-mode reconfigurable lowpass/complex bandpass CT ΣΔ modulator for short range wireless receiver.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A 0.1-1.5G SDR transmitter with two-stage harmonic rejection power mixer in 65-nm CMOS.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Analysis and design of a high linearity quadrature demodulator based on SiGe BiCMOS process.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A 60-GHz wireless transceiver with dual-mode power amplifier for IEEE 802.11ad in 65nm CMOS.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
A Reconfigurable Dual-Mode CMOS Power Amplifier With Integrated T/R Switch for 0.1-1.5-GHz Multistandard Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A 0.1-5.0 GHz Reconfigurable Transmitter With Dual-Mode Power Amplifier and Digitally-Assisted Self-Calibration for Private Network Communications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Microelectron. J., 2014
-80dBm∼0dBm dynamic range, 30mV/dB detection sensitivity piecewise RSSI for SDR/CR receivers.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Scalable behavior modeling for SCR based ESD protection structures for circuit simulation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
An efficiency-enhanced 2.4GHz stacked CMOS power amplifier with mode switching scheme for WLAN applications.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
A 0.1-1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
A fully-integrated reconfigurable dual-band transceiver for short range wireless communication in 180nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO.
IEEE J. Solid State Circuits, 2013
IEEE J. Solid State Circuits, 2013
Lifetime tracing of cardiopulmonary sounds with ultra-low-power sound sensor stick connected to wireless mobile network.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
A half rate CDR with DCD cleaning up and quadrature clock calibration for 20Gbps 60GHz communication in 65nm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A multi-mode complex bandpass filter with gm-assisted power optimization and I/Q calibration.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A 180nm fully-integrated dual-channel reconfigurable receiver for GNSS interoperations.
Proceedings of the ESSCIRC 2013, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Microelectron. J., 2012
A hybrid approach to I/Q imbalance self-calibration in reconfigurable low-IF receivers.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Power-scalable multi-mode reconfigurable continuous-time lowpass/quadrature bandpass sigma-delta modulator for zero/low-IF receivers.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A 0.1~4GHz receiver and 0.1~6GHz transmitter with reconfigurable 10~100MHz signal bandwidth in 65nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
A 65 nm CMOS fully-integrated dynamic reconfigurable differential power amplifier with high gain in both bands.
Microelectron. J., 2011
Ultra-high-frequency radio frequency identification reader receiver with 10 dBm input P1 dB and -74 dBm sensitivity in 0.18 μm CMOS.
IET Circuits Devices Syst., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
A 0.18-muhboxm CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Microelectron. J., 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Low-Power Transceiver Analog Front-End Circuits for Bidirectional High Data Rate Wireless Telemetry in Medical Endoscopy Applications.
IEEE Trans. Biomed. Eng., 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Process Variation Compensation of a 2.4GHz LNA in 0.18um CMOS Using Digitally Switchable Capacitance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
New implementation of injection locked technique and its application to low phase noise quadrature oscillators.
Microelectron. J., 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A 2.4GHz low power wireless transceiver analog front-end for endoscopy capsule system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2003
A 1.8V 2.4GHz CMOS on-chip impedance matching low noise amplifier for WLAN applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003