Bao Liu

According to our database, Bao Liu authored at least 48 papers between 2001 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2015

Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation.

Bao Liu, Lu Wang

IEEE Trans. Very Large Scale Integr. Syst., 2015

Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design.

Vivek K. De, Andrew B. Kahng, Tanay Karnik, Bao Liu, Milad Maleki, Lu Wang

ACM J. Emerg. Technol. Comput. Syst., 2015

Reconfiguration-Based VLSI Design for Security.

Bao Liu, Brandon Wang

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Crosstalk-aware signal probability-based dynamic statistical timing analysis.

Yao Chen, Andrew B. Kahng, Bao Liu, Wenjun Wang

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014

Power/ground supply voltage variation-aware delay test pattern generation.

Lu Wang, Xutao Wang, Milad Maleki, Bao Liu

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Input-aware statistical timing analysis for VLSI delay test and average design.

Bao Liu

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Testing, diagnosis and repair methods for NBTI-induced SRAM faults.

Bao Liu, Chiung-Hung Chen

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks.

Bao Liu, Brandon Wang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Variable latency VLSI design based on timing analysis, delay ATPG, and completion prediction.

Bao Liu, Lu Wang, Juan Portillo

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Input-aware statistical timing analysis-based delay test pattern generation.

Bao Liu, Lu Wang

Proceedings of the International Symposium on Quality Electronic Design, 2013

2012

Resilient and adaptive performance logic.

Bao Liu, Xuemei Chen, Fiona Teshome

ACM J. Emerg. Technol. Comput. Syst., 2012

Delay insensitive code-based timing and soft error-resilient and adaptive-performance logic.

Bao Liu, Xuemei Chen, Fiona Teshome

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Minimum logic of guaranteed single soft error resilience based on group distance-two code.

Bao Liu, Lu Wang

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011

Statistical full-chip dynamic power estimation considering spatial correlations.

Zhigang Hao, Ruijing Shen, Sheldon X.-D. Tan, Bao Liu, Guoyong Shi, Yici Cai

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010

Architecture exploration of crossbar-based nanoscale reconfigurable computing platforms.

Bao Liu

Nano Commun. Networks, 2010

Voltage-controlled nano-addressing for nanosystem communication.

Bao Liu

Nano Commun. Networks, 2010

Error-detecting/correcting-code-based self-checked/corrected/timed circuits.

Bao Liu

Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2009

Reduced Voltage Scaling in Clock Distribution Networks.

Khader Mohammad, Ayman Dodin, Bao Liu, Sos S. Agaian

VLSI Design, 2009

Energy Efficient Swing signal generation circuits for clock distribution networks.

Khader Mohammad, Bao Liu, Sos S. Agaian

Proceedings of the IEEE International Conference on Systems, 2009

Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution.

Bao Liu

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Robust differential asynchronous nanoelectronic circuits.

Bao Liu

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Defect Mapping and Adaptive Configuration of Nanoelectronic Circuits Based on a CNT Crossbar Nano-Architecture.

Bao Liu

Proceedings of the 18th International Conference on Computer Communications and Networks, 2009

Analysis and extraction of parametric variation effects on microelectrofluidics-based biochips.

Bao Liu

Proceedings of the 2009 IEEE International Behavioral Modeling and Simulation Workshop, 2009

Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture.

Bao Liu

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A Voltage Controlled Nano Addressing Circuit.

Bao Liu

Proceedings of the Nano-Net - Third International ICST Conference, 2008

Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression.

Bao Liu

Proceedings of the Design, Automation and Test in Europe, 2008

Signal Probability Based Statistical Timing Analysis.

Bao Liu

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs.

Bao Liu, Sheldon X.-D. Tan

IEEE Trans. Very Large Scale Integr. Syst., 2007

Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement.

Andrew B. Kahng, Bao Liu, Qinke Wang

IEEE Trans. Very Large Scale Integr. Syst., 2007

Statistical Timing Analysis in the Presence of Signal-Integrity Effects.

Andrew B. Kahng, Bao Liu, Xu Xu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations.

Bao Liu

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Analytical thermal placement for VLSI lifetime improvement and minimum performance variation.

Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu

Proceedings of the 25th International Conference on Computer Design, 2007

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield.

Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Statistical crosstalk aggressor alignment aware interconnect delay calculation.

Andrew B. Kahng, Bao Liu, Xu Xu

Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Constructing Current-Based Gate Models Based on Existing Timing Library.

Andrew B. Kahng, Bao Liu, Xu Xu

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching.

Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Efficient decoupling capacitor planning via convex programming methods.

Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan

Proceedings of the 2006 International Symposium on Physical Design, 2006

Statistical gate delay calculation with crosstalk alignment consideration.

Andrew B. Kahng, Bao Liu, Xu Xu

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005

Supply Voltage Degradation Aware Analytical Placement.

Andrew B. Kahng, Bao Liu, Qinke Wang

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004

Nontree routing for reliability and yield improvement [IC layout].

Andrew B. Kahng, Bao Liu, Ion I. Mandoiu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003

Minimum buffered routing with bounded capacitive load for slew rate and reliability control.

Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

On the skew-bounded minimum-buffer routing tree problem.

Christoph Albrecht, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization.

Andrew B. Kahng, Bao Liu

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

2002

Toward better wireload models in the presence of obstacles.

Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt

IEEE Trans. Very Large Scale Integr. Syst., 2002

Non-tree routing for reliability and yield improvement.

Andrew B. Kahng, Bao Liu, Ion I. Mandoiu

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001

Interconnect implications of growth-based structural models for VLSI circuits.

Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Buffered Steiner trees for difficult instances.

Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia

Proceedings of the 2001 International Symposium on Physical Design, 2001

Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control.

Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001