Banafsheh S. Latibari

Orcid: 0000-0003-3735-9191

According to our database1, Banafsheh S. Latibari authored at least 10 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
Cross-core Data Sharing for Energy-efficient GPUs.
ACM Trans. Archit. Code Optim., September, 2024

Optimized and Automated Secure IC Design Flow: A Defense-in-Depth Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024

Automated Hardware Logic Obfuscation Framework Using GPT.
CoRR, 2024

Securing On-Chip Learning: Navigating Vulnerabilities and Potential Safeguards in Spiking Neural Network Architectures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

IRET: Incremental Resolution Enhancing Transformer.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023
Hardware Trojan Detection Using Machine Learning: A Tutorial.
ACM Trans. Embed. Comput. Syst., 2023

HW-V2W-Map: Hardware Vulnerability to Weakness Mapping Framework for Root Cause Analysis with GPT-assisted Mitigation Suggestion.
CoRR, 2023

Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop Minimization.
IEEE Access, 2023

2022
Adaptive-Gravity: A Defense Against Adversarial Samples.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022


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