Balwinder Raj

According to our database, Balwinder Raj authored at least 23 papers between 2010 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Design and simulation of junctionless nanowire tunnel field effect transistor for highly sensitive biosensor.

Parveen Kumar, Balwinder Raj

Microelectron. J., 2023

2022

Spintronics Based Non-Volatile MRAM for Intelligent Systems: Memory for Intelligent Systems Design.

Parul Sharma, Balwinder Raj, Sandeep Singh Gill

Int. J. Semantic Web Inf. Syst., January, 2022

2021

Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor.

Tulika Chawla, Mamta Khosla, Balwinder Raj

Microelectron. J., 2021

Comparative radio-frequency and crosstalk analysis of carbon-based nano-interconnects.

Manjit Kaur, Neena Gupta, Sanjeev Kumar, Balwinder Raj, Arun K. Singh

IET Circuits Devices Syst., 2021

2020

SOI FinFET for Computer Networks and Cyber Security Systems.

Neeraj Jain, Balwinder Raj

Proceedings of the Handbook of Computer Networks and Cyber Security, 2020

2019

IoT-Based Ambient Intelligence Microcontroller for Remote Temperature Monitoring.

Balwinder Raj, Jeetendra Singh, Santosh Kumar Vishvakarma, Shailesh Singh Chouhan

Proceedings of the Guide to Ambient Intelligence in the IoT Environment, 2019

Design and Investigation of 7T2M-NVSRAM With Enhanced Stability and Temperature Impact on Store/Restore Energy.

Jeetendra Singh, Balwinder Raj

IEEE Trans. Very Large Scale Integr. Syst., 2019

Design and analysis of dynamically configurable electrostatic doped carbon nanotube tunnel FET.

Amandeep Singh, Mamta Khosla, Balwinder Raj

Microelectron. J., 2019

A low leakage TG-CNTFET-based inexact full adder for low power image processing applications.

Candy Goyal, Jagpal Singh Ubhi, Balwinder Raj

Int. J. Circuit Theory Appl., 2019

2018

Fault-tolerant design and analysis of QCA-based circuits.

Gurmohan Singh, Balwinder Raj, Rakesh Kumar Sarin

IET Circuits Devices Syst., 2018

2017

Design and analysis of area efficient QCA based reversible logic gates.

Gurmohan Singh, Rakesh Kumar Sarin, Balwinder Raj

Microprocess. Microsystems, 2017

2016

A Gaussian approach for analytical subthreshold current model of cylindrical nanowire FET with quantum mechanical effects.

Sanjeev Kumar Sharma, Balwinder Raj, Mamta Khosla

Microelectron. J., 2016

CNTFET modeling and low power SRAM cell design.

Amandeep Singh, Mamta Khosla, Balwinder Raj

Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

2015

Modeling of DG-Tunnel FET for low power VLSI circuit design.

Sunil Kumar, Balwinder Raj

Proceedings of the Eighth International Conference on Contemporary Computing, 2015

Comparative analysis of carbon nanotube field effect transistors.

Amandeep Singh, Mamta Khosla, Balwinder Raj

Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

Performance enhancement of junctionless nanowire FET with laterally graded channel doping and high-K spacers.

Sanjeev Kumar Sharma, Balwinder Raj, Mamta Khosla

Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

Thermally aware modeling and performance for MWCNT bundle as VLSI interconnects for high performance integrated circuits.

Karmjit Singh Sandha, Balwinder Raj

Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

2014

PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits.

Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj

Microelectron. Reliab., 2014

2012

Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders.

Shashikant Sharma, Manisha Pattanaik, Balwinder Raj

Proceedings of the International Symposium on Electronic System Design, 2012

Analyzing Different Mode FinFET Based Memory cell at different power supply for Leakage Reduction.

Sushil Bhushan, Saurabh Khandelwal, Balwinder Raj

Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012), 2012

2011

Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology.

Balwinder Raj, Jatin Mitra, Deepak Kumar Bihani, V. Rangharajan, Ashok K. Saxena, Sudeb Dasgupta

J. Low Power Electron., 2011

Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach.

Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta

Proceedings of the International Conference on Soft Computing for Problem Solving (SocProS 2011) December 20-22, 2011, 2011

2010

Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach.

Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta

Proceedings of the Fourth UKSim European Symposium on Computer Modeling and Simulation, 2010