Balaram Sinharoy

According to our database, Balaram Sinharoy authored at least 29 papers between 1992 and 2021.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2021

Energy Efficiency Boost in the AI-Infused POWER10 Processor.

Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2015

Advanced features in IBM POWER8 systems.

Balaram Sinharoy, Randal C. Swanberg, Naresh Nayar, Bruce G. Mealey, Jeffrey Stuecheli, Berni Schiefer, Jens Leenstra, Joefon Jann, P. Oehler, D. Levitan, S. Eisen, D. Sanner, Thomas Pflueger, Cédric Lichtenau, W. E. Hall, T. Block

IBM J. Res. Dev., 2015

IBM POWER8 processor core microarchitecture.

Balaram Sinharoy, James Van Norstrand, Richard J. Eickemeyer, Hung Q. Le, Jens Leenstra, Dung Q. Nguyen, B. Konigsburg, K. Ward, M. D. Brown, José E. Moreira, D. Levitan, S. Tung, David Hrusecky, James W. Bishop, Michael Gschwind, Maarten Boersma, Michael Kroener, Markus Kaltenbach, Tejas Karkhanis, K. M. Fernsler

IBM J. Res. Dev., 2015

2014

The POWER8^TM processor: Designed for big data, analytics, and cloud environments.

Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2011

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.

Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban

IEEE J. Solid State Circuits, 2011

2010

Power7: IBM's Next-Generation Server Processor.

Ronald N. Kalla, Balaram Sinharoy, William J. Starke, Michael S. Floyd

IEEE Micro, 2010

The implementation of POWER7^TM: A highly parallel and scalable multi-core high-end server processor.

Dieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, Roland Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott A. Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

POWER7 multi-core processor design.

Balaram Sinharoy

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

POWER7: IBM's next generation server processor.

Ronald N. Kalla, Balaram Sinharoy

Proceedings of the 2009 IEEE Hot Chips 21 Symposium (HCS), 2009

2005

POWER5 system microarchitecture.

Balaram Sinharoy, Ronald N. Kalla, Joel M. Tendler, Richard J. Eickemeyer, Jody B. Joyner

IBM J. Res. Dev., 2005

Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.

Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004

IBM Power5 Chip: A Dual-Core Multithreaded Processor.

Ronald N. Kalla, Balaram Sinharoy, Joel M. Tendler

IEEE Micro, 2004

Design and implementation of the POWER5 microprocessor.

Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip J. Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson

Proceedings of the 41th Design Automation Conference, 2004

2002

POWER4 system microarchitecture.

Joel M. Tendler, J. Steve Dodson, J. S. Fields Jr., Hung Q. Le, Balaram Sinharoy

IBM J. Res. Dev., 2002

A microarchitectural-level step-power analysis tool.

Wael El-Essawy, David H. Albonesi, Balaram Sinharoy

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

1999

Compiler optimization to improve data locality for processor multithreading.

Balaram Sinharoy

Sci. Program., 1999

1997

Parallelising Compilers and Systems.

Balaram Sinharoy, Boleslaw K. Szymanski

Parallel Algorithms Appl., 1997

Introduction: Special Issue on Optimising Compilers for Parallel Languages.

Balaram Sinharoy, Boleslaw K. Szymanski

Parallel Algorithms Appl., 1997

Optimized Thread Creation for Processor Multithreading.

Balaram Sinharoy

Comput. J., 1997

1996

Improving Software MP Efficiency for Shared Memory Systems.

Balaram Sinharoy, Rama Govindaraju

Proceedings of the 29th Annual Hawaii International Conference on System Sciences (HICSS-29), 1996

1995

Simultaneous Parallel Reduction on SIMD Machines.

Boleslaw K. Szymanski, William Maniatty, Balaram Sinharoy

Parallel Process. Lett., 1995

Announcement of a Special Issue of the Journal of Parallel Algorithms and Applications on Optimising Compilers for Parallel Languages.

Balaram Sinharoy, Boleslaw K. Szymanski

Parallel Algorithms Appl., 1995

Compiling for Multithreaded Multicomputer.

Balaram Sinharoy

Proceedings of the Languages, 1995

1994

Compiler Technology for Parallel Scientific Computation.

Can C. Özturan, Balaram Sinharoy, Boleslaw K. Szymanski

Sci. Program., 1994

Finding Optimum Wavefront of Parallel Computation.

Balaram Sinharoy, Boleslaw K. Szymanski

Parallel Algorithms Appl., 1994

Data and Task Alignment in Distributed Memory Architectures.

Balaram Sinharoy, Boleslaw K. Szymanski

J. Parallel Distributed Comput., 1994

1992

Corrigenda: Complexity of the Closest Vector Problem in a Lattice Generated by (0, 1)-Matrix.

Boleslaw K. Szymanski, Balaram Sinharoy

Inf. Process. Lett., 1992

Complexity of the Closest Vector Problem in a Lattice Generated by (0, 1)-Matrix.

Boleslaw K. Szymanski, Balaram Sinharoy

Inf. Process. Lett., 1992

Efficiency of Data Alignment on Maspar.

William Maniatty, Boleslaw K. Szymanski, Balaram Sinharoy

Proceedings of the 2nd SIGPLAN Workshop on Languages, Compilers, and Run-Time Environments for Distributed Memory Multiprocessors, Boulder, Colorado, September 30, 1992