Balakrishna Jayadev

According to our database, Balakrishna Jayadev authored at least 3 papers between 2016 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features.

Amitava Majumdar, Balakrishna Jayadev

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs.

Amitava Majumdar, Balakrishna Jayadev, Da Cheng, Albert Lin

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Application debug in FPGAs in the presence of multiple asynchronous clocks.

Georgios Tzimpragos, Da Cheng, Stephanie Tapp, Balakrishna Jayadev, Amitava Majumdar

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016