Balaji Venu

According to our database, Balaji Venu authored at least 10 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Characterization of a Coherent Hardware Accelerator Framework for SoCs.

Guillem López-Paradís, Balaji Venu, Adrià Armejach, Miquel Moretó

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

2022

Industrial Challenge 2022: A High-Performance Real-Time Case Study on Arm.

Matteo Andreozzi, Giacomo Gabrielli, Balaji Venu, Giacomo Travaglini

Proceedings of the 34th Euromicro Conference on Real-Time Systems, 2022

2018

The Arm Triple Core Lock-Step (TCLS) Processor.

Xabier Iturbe, Balaji Venu, Emre Ozer, Jean-Luc Poupat, Gregoire Gimenez, Hans-Ulrich Zurek

ACM Trans. Comput. Syst., 2018

Addressing Functional Safety Challenges in Autonomous Vehicles with the Arm TCL S Architecture.

Xabier Iturbe, Balaji Venu, Juergen Jagst, Emre Ozer, Peter Harrod, Chris Turner, John Penton

IEEE Des. Test, 2018

Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems.

Emre Ozer, Balaji Venu, Xabier Iturbe, Shidhartha Das, Spyros Lyberis, John Biggs, Peter Harrod, John Penton

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

2017

A "high resilience" mode to minimize soft error vulnerabilities in ARM cortex-R CPU pipelines: work-in-progress.

Xabier Iturbe, Balaji Venu, John Penton, Emre Ozer

Proceedings of the 2017 International Conference on Compilers, 2017

2016

A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications.

Xabier Iturbe, Balaji Venu, Emre Ozer, Shidhartha Das

Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2016

Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU.

Xabier Iturbe, Balaji Venu, Emre Ozer

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2012

Formal verification methodology considerations for network on chips.

Balaji Venu, Ashwani Singh

Proceedings of the 2012 International Conference on Advances in Computing, 2012

2011

Multi-core processors - An overview

Balaji Venu

CoRR, 2011