Balaji Jayaraman
Orcid: 0000-0003-3675-9396
According to our database1,
Balaji Jayaraman
authored at least 11 papers
between 2007 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2021
Cascaded and Non-Cascaded Incremental Nonlinear Dynamic Inversion Flight Control Applied to a Light Aircraft.
Proceedings of the 2021 Australian & New Zealand Control Conference, 2021
2020
Assessment of end-to-end and sequential data-driven learning for non-intrusive modeling of fluid flows.
Adv. Comput. Math., 2020
2019
2018
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.
IEEE J. Solid State Circuits, 2018
2017
Proceedings of the Advances in Robotics, 2017
2016
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2012
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
2010
J. Comput. Phys., 2010
2009
Performance Analysis of Subthreshold Cascode Current Mirror in 130 nm CMOS Technology.
J. Low Power Electron., 2009
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007