Bala Haran

According to our database, Bala Haran authored at least 5 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Material, Process and System Level Analysis for Parasitic Reduction of Next Generation Logic Technology in Conjunction with Backside Power Delivery.

Ashish Pal, Sefa Dag, Pratik B. Vyas, Gregory Costrini, Vinod Reddy, Veeraraghavan Basker, Allen Yeong, Benjamin Colombeau, Bala Haran, Subi Kengeri, El Mehdi Bazizi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Gate-All-Around SRAM: Performance Investigation and Optimization Towards Vccmin Scaling.

Pratik B. Vyas, Ashish Pal, Gregory Costrini, Benjamin Colombeau, Bala Haran, Subi Kengeri, El Mehdi Bazizi

Proceedings of the IEEE International Memory Workshop, 2024

2023

Contact Cavity Shaping and Selective SiGe: B Low-Temperature Epitaxy Process Solution for sub 10^-9 Ω.cm² Contact Resistivity in Nonplanar FETs.

N. Breil, B.-C. Lee, J. Avila Avendano, J. Jewell, M. Vellaikal, E. Newman, E. M. Bazizi, Ashish Pal, L. Liu, Oleg Gluschenkov, A. Greene, S. Mochizuki, Nicolas Loubet, Benjamin Colombeau, Bala Haran

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Materials Enabled Memory Scaling and New Architectures.

Zhijun Chen, Fred Fishburn, Chang Seok Kang, Sony Varghese, Bala Haran

Proceedings of the IEEE International Memory Workshop, 2023

2017

Interface engineering of Si1-xGex gate stacks for high performance dual channel CMOS.

ChoongHyun Lee, Richard G. Southwick, Shogo Mochizuki, Paul Jamison, Ruqiang Bao, Rajan Pandey, Aniruddha Konar, Takashi Ando, Vijay Narayanan, Bala Haran, Hemanth Jagannathan

Proceedings of the 12th IEEE International Conference on ASIC, 2017