Baishakhi Rani Biswas

According to our database, Baishakhi Rani Biswas authored at least 4 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Systematic Generation of Memristor-Transistor Single-Phase Combinational Logic Cells.

Baishakhi Rani Biswas, Claire Yuan, Fangzhou Wang, Sandeep Gupta

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm² Active Area in 12nm FinFET.

Qiaochu Zhang, Shiyu Su, Baishakhi Rani Biswas, Sandeep Gupta, Mike Shuo-Wei Chen

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2022

Memristor-Specific Failures: New Verification Methods and Emerging Test Problems.

Baishakhi Rani Biswas, Sandeep Gupta

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

2017

Memristor-Based Low-Power High-Speed Nonvolatile Hybrid Memory Array Design.

Khandoker Asif Faruque, Baishakhi Rani Biswas, A. B. M. Harun-ur Rashid

Circuits Syst. Signal Process., 2017