Bahram Pouya

According to our database, Bahram Pouya authored at least 9 papers between 1997 and 2004.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2004

Test data compression technique for embedded cores using virtual scan chains.

Abhijit Jas, Bahram Pouya, Nur A. Touba

IEEE Trans. Very Large Scale Integr. Syst., 2004

2001

Reducing Power Dissipation during Test Using Scan Chain Disable.

Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000

Virtual Scan Chains: A Means for Reducing Scan Length in Cores.

Abhijit Jas, Bahram Pouya, Nur A. Touba

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Optimization trade-offs for vector volume and test power.

Bahram Pouya, Alfred L. Crouch

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1998

Synthesis of Zero-Aliasing Elementary-Tree Space Compactors.

Bahram Pouya, Nur A. Touba

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

BETSY: synthesizing circuits for a specified BIST environment.

Zhe Zhao, Bahram Pouya, Nur A. Touba

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

Using Partial Isolation Rings to Test Core-Based Designs.

Nur A. Touba, Bahram Pouya

IEEE Des. Test Comput., 1997

Testing Embedded Cores Using Partial Isolation Rings.

Nur A. Touba, Bahram Pouya

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Modifying User-Defined Logic for Test Access to Embedded Cores.

Bahram Pouya, Nur A. Touba

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997