Baher Haroun

According to our database, Baher Haroun authored at least 35 papers between 1988 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A Sub-THz CMOS Transceiver IC and System for Medium-Reach Guided Wave and Short-Reach Wireless Communication Links.

Swaminathan Sankaran, Gerd Schuppener, Juan Herbsommer, Bradley Kramer, Hassan Ali, Robert Payne, Carole Rush, Baher Haroun, Nirmal Warke

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

2023

A 0.5-to-400MHz Programmable BAW Oscillator with Fractional Output Divider Achieving 4ppm Frequency Stability over Temperature and <95fs Jitter.

Subhashish Mukherjee, Yogesh Darwhekar, Jayawardan Janardhanan, Peeyoosh Mirajkar, Raghavendra Reddy, Harish Ramesh, Bichoy Bahr, Jagdish Chand, Uday Meda, Baher Haroun, Shankar Karantha, Ernest Ting-Ta Yen, Keegan Martin, Daniel Gan, Amin Sijelmassi, Sankaran Aniruddhan

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design.

Athanasios Ramkaj, Michael Perrott, Baher Haroun, Boris Murmann

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

A Sub-100 Fs RMS_jitter 20 GHz Fractional-N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference.

Sachin Kalia, Salvatore Finocchiaro, Tolga Dinc, Bichoy Bahr, Ashwin Raghunathan, Gerd Schuppener, Siraj Akhtar, Tobias Fritz, Baher Haroun, Benjamin Cook, Swaminathan Sankaran

IEEE J. Solid State Circuits, 2022

A Duty-Cycled Integrated-Fluxgate Magnetometer for Current Sensing.

Preet Garcha, Viola Schaffer, Baher Haroun, Srinath Ramaswamy, Jim Wieser, Jeffrey H. Lang, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2022

High-Efficiency Class-E Power Amplifiers for mmWave Radar Sensors: Design and Implementation.

Tolga Dinc, Sachin Kalia, Siraj Akhtar, Baher Haroun, Benjamin Cook, Swaminathan Sankaran

IEEE J. Solid State Circuits, 2022

2021

A 770 kS/s Duty-Cycled Integrated-Fluxgate Magnetometer for Contactless Current Sensing.

Preet Garcha, Viola Schaffer, Baher Haroun, Srinath Ramaswamy, Jim Wieser, Jeffrey H. Lang, Anantha P. Chandrakasan

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

An Ultra-Low Close-In Phase Noise Series-Resonance BAW Oscillator in a 130-nm BiCMOS process.

Sachin Kalia, Bichoy Bahr, Tolga Dinc, Baher Haroun, Swaminathan Sankaran

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020

3.1 An Integrated BAW Oscillator with <±30ppm Frequency Stability Over Temperature, Package Stress, and Aging Suitable for High-Volume Production.

Danielle Griffith, Ernest Ting-Ta Yen, Kaichien Tsai, Habeeb Ur Rahman Mohammed, Baher Haroun, Ali Kiaei, Ahmad Bahai

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018

Autonomous Vehicles SEnsor Needs.

Baher Haroun

Proceedings of the 48th European Solid-State Device Research Conference, 2018

2017

A 29.5 dBm Class-E Outphasing RF Power Amplifier With Efficiency and Output Power Enhancement Circuits in 45nm CMOS.

Aritra Banerjee, Rahmi Hezar, Lei Ding, Baher Haroun

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2015

A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications.

Rahmi Hezar, Lei Ding, Aritra Banerjee, Joonhoi Hur, Baher Haroun

IEEE J. Solid State Circuits, 2015

A 25 dBm Outphasing Power Amplifier With Cross-Bridge Combiners.

Lei Ding, Joonhoi Hur, Aritra Banerjee, Rahmi Hezar, Baher Haroun

IEEE J. Solid State Circuits, 2015

2014

A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS.

Brian P. Ginsburg, Srinath Ramaswamy, Vijay Rentala, Eunyoung Seok, Swaminathan Sankaran, Baher Haroun

IEEE J. Solid State Circuits, 2014

A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS.

Aritra Banerjee, Rahmi Hezar, Lei Ding, Nathan Schemm, Baher Haroun

Proceedings of the ESSCIRC 2014, 2014

2013

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops.

Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012

Low power ADC's for wireless communications.

Vijay Rentala, Venkatesh Srinivasan, Victoria Wang, Srinath Ramaswamy, Baher Haroun, Marco Corsi

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A 20mW 61dB SNDR (60MHz BW) 1b 3^rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS.

Venkatesh Srinivasan, Victoria Wang, Patrick Satarzadeh, Baher Haroun, Marco Corsi

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Session 16 overview: Switching power control techniques: Analog subcommittee.

Baher Haroun, Gyu-Hyeong Cho

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2010

A 0.16mm² completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS.

Yogesh K. Ramadass, Ayman A. Fayed, Baher Haroun, Anantha P. Chandrakasan

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 110dB SNR and 0.5mW current-steering audio DAC implemented in 45nm CMOS.

Rahmi Hezar, Lars Risbo, Halil Kiper, Mounir Fares, Baher Haroun, Gangadhar Burra, Gabriel Gomez

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2006

A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS.

Jinseok Koh, Gabriel Gomez, Khurram Muhammad, Robert Bogdan Staszewski, Baher Haroun

EURASIP J. Wirel. Commun. Netw., 2006

2002

An embedded 0.8 V/480 μW 6b/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique.

Jerry (Heng-Chih) Lin, Baher Haroun

IEEE J. Solid State Circuits, 2002

A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities.

Prasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

1995

Floorplanning with Datapath Optimization.

Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses.

Baher Haroun, Behzad Sajjadi

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994

A Floorplanner driven by Structural & Timing Constraints.

Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic.

Baher Haroun, Chao Hua Wu

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI Systems.

Reza Golshan, Baher Haroun

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs.

Baher Haroun, Behzard Sajjadi

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1992

Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks.

Baher Haroun, Elie Torbey

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Power estimation tool for sub-micron CMOS VLSI circuits.

F. Rouatbi, Baher Haroun, Asim J. Al-Khalili

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1989

SPAID: an architectural synthesis tool for DSP custom applications.

Baher Haroun, Mohamed I. Elmasry

IEEE J. Solid State Circuits, April, 1989

Architectural synthesis for DSP silicon compilers.

Baher Haroun, Mohamed I. Elmasry

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988

Automatic synthesis of a multi-bus architecture for DSP.

Baher Haroun, Mohamed I. Elmasry

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988