Bahar Jalali Farahani

According to our database, Bahar Jalali Farahani authored at least 7 papers between 2005 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

A fully integrated scalable W-band phased-array module with integrated antennas, self-alignment and self-test.

Shahriar Shahramian, Mike Holyoak, Amit Singh, Bahar Jalali Farahani, Yves Baeyens

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2011

An online fully-digital calibration of leakage noise in MASH continuous time ΔΣ modulators.

Sudharsan Kanagaraj, Bahar Jalali Farahani

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2009

A 14-b 32MS/s Pipelined ADC with Novel Fast-convergence Comprehensive Background Calibration.

Anand Meruva, Bahar Jalali Farahani

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Low Power High Performance Digitally Assisted Pipelined ADC.

Bahar Jalali Farahani, Anand Meruva

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007

Adaptive Noise Cancellation Techniques in Sigma-Delta Analog-to-Digital Converters.

Bahar Jalali Farahani, Mohammed Ismail

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Digital Background Calibration of Higher Order Nonlinearities in Pipelined ADCs.

Anand Meruva, Bahar Jalali Farahani

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005

Adaptive digital techniques to suppress quantization noise of Sigma Delta analog to digital converters.

Bahar Jalali Farahani, Mohammed Ismail

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005