Bahar Asgari

Orcid: 0000-0003-2305-9892

According to our database1, Bahar Asgari authored at least 30 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Endor: Hardware-Friendly Sparse Format for Offloaded LLM Inference.
CoRR, 2024

Misam: Using ML in Dataflow Selection of Sparse-Sparse Matrix Multiplication.
CoRR, 2024

2023
Memory-Based Computing for Energy-Efficient AI: Grand Challenges.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Spica: Exploring FPGA Optimizations to Enable an Efficient SpMV Implementation for Computations at Edge.
Proceedings of the IEEE International Conference on Edge Computing and Communications, 2023

Context-Aware Task Handling in Resource-Constrained Robots with Virtualization.
Proceedings of the IEEE International Conference on Edge Computing and Communications, 2023

Creating Robust Deep Neural Networks with Coded Distributed Computing for IoT.
Proceedings of the IEEE International Conference on Edge Computing and Communications, 2023

2022
Maia: Matrix Inversion Acceleration Near Memory.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021
Efficiently Accelerating Sparse Problems by Enabling Stream Accesses to Memory using Hardware/Software Techniques.
PhD thesis, 2021

MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System.
J. Signal Process. Syst., 2021

Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware.
IEEE Trans. Computers, 2021

Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads.
Proceedings of the IEEE International Symposium on Workload Characterization, 2021

FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Quantifying the design-space tradeoffs in autonomous drones.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads.
CoRR, 2020

Edge-Tailored Perception: Fast Inferencing in-the-Edge with Efficient Model Distribution.
CoRR, 2020

MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic Architecture.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Proposing a Fast and Scalable Systolic Array for Matrix Multiplication.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to Memory.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse Algebra.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays.
IEEE Micro, 2019

Characterizing the Deployment of Deep Neural Networks on Commercial Edge Devices.
Proceedings of the IEEE International Symposium on Workload Characterization, 2019

Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNs.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems.
CoRR, 2018

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

2017
Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file.
IET Comput. Digit. Tech., 2017

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology.
Turkish J. Electr. Eng. Comput. Sci., 2017

Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017


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