Babita Jajodia

According to our database1, Babita Jajodia authored at least 10 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2022
Optimized Hardware Implementation of Vedic Binary Multiplier using Nikhilam Sutra on FPGA.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

FPGA Implementation of Hybrid Karatsuba Multiplications for NIST Post-Quantum Cryptographic Hardware Primitives.
Proceedings of the 19th International SoC Design Conference, 2022

Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications on FPGA.
Proceedings of the 19th International SoC Design Conference, 2022

ART-MAC: Approximate Rounding and Truncation based MAC Unit for Fault-Tolerant Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Towards an Optimal Hybrid Algorithm for EV Charging Stations Placement using Quantum Annealing and Genetic Algorithms.
CoRR, 2021

Efficient Hardware Implementation of Cube Architecture using Yavadunam Sutra on FPGA.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2018
Mixed-signal demodulator for IEEE 802.15.6 IR-UWB WBAN energy detection-based receiver.
IET Circuits Devices Syst., 2018

2014
A Six-Segment SRRC Pulse Generator for IEEE 802.15.6 WBAN Standard.
Proceedings of the 9th International Conference on Body Area Networks, 2014


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