B. Yamuna

Orcid: 0000-0002-5272-5383

According to our database1, B. Yamuna authored at least 11 papers between 2012 and 2022.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A Generic Reliability Based Direct Decoding Algorithm for Turbo Codes.
Wirel. Pers. Commun., 2022

2020
A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study.
PeerJ Comput. Sci., 2020

A novel reliability-based high performance decoding algorithm for short block length turbo codes.
Int. J. Ad Hoc Ubiquitous Comput., 2020

2019
Effect of sign-bit-flipping trojan on turbo coded communication systems.
Proceedings of the 20th International Conference on Distributed Computing and Networking, 2019

2018
Effect of hardware Trojans on the performance of a coded communication system.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Low Power and Area Efficient Max-log -MAP Decoder.
Proceedings of the 2018 International Conference on Advances in Computing, 2018

FPGA Implementation of an Efficient High Speed Max-log-MAP Decoder.
Proceedings of the 2018 International Conference on Advances in Computing, 2018

2017
A low complex turbo decoding algorithm with early iteration termination.
Proceedings of the 2017 International Conference on Advances in Computing, 2017

2016
Reliability level list-based decoding of multilevel modulated block codes.
Int. J. Inf. Commun. Technol., 2016

2014
A minimal search soft decision list decoding algorithm for Reed-Solomon codes.
Int. J. Inf. Commun. Technol., 2014

2012
A Reliability Level List based SDD Algorithm for Binary Cyclic Block Codes.
Int. J. Comput. Commun. Control, 2012


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