B. Venkataramani

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2023
A Novel Feature Enhancement Technique for ECG Arrhythmia Classification Using Discrete Anamorphic Stretch Transform.
Circuits Syst. Signal Process., 2023

2022
A novel ECG signal compression using wavelet and discrete anamorphic stretch transforms.
Biomed. Signal Process. Control., 2022

2021
A Low-Noise Area-Efficient Current Feedback Instrumentation Amplifier.
Circuits Syst. Signal Process., 2021

2020
A novel programmable attenuator based low G<sub>m</sub>-OTA for biomedical applications.
Microelectron. J., 2020

High-performance asynchronous pipeline using embedded delay element.
Microprocess. Microsystems, 2020

Highly linear inductorless asymmetric capacitive cross-coupled wideband balun-LNAs.
Comput. Electr. Eng., 2020

2019
Wideband Balun-LNAs using asymmetric CCC technique for WLAN and mobile WiMAX applications.
Microelectron. J., 2019

Reconfigurable low voltage low power dual-band self-cascode current-reuse quasi-differential LNA for 5G.
Microelectron. J., 2019

2017
Erratum to: A 1-V 2.4 GHz Low-Power CMOS LNA Using Gain-Boosting and Derivative Superposition Techniques for WSN.
Wirel. Pers. Commun., 2017

A 1-V 2.4 GHz Low-Power CMOS LNA Using Gain-Boosting and Derivative Superposition Techniques for WSN.
Wirel. Pers. Commun., 2017

Low Power Data Driven Conditional Precharge Dynamic Flip Flop.
J. Low Power Electron., 2017

FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFT.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

A Novel Opamp and Capacitor Sharing 10 Bit 20 MS/s Low Power Pipelined ADC in 0.18µm CMOS Technology.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
A high linearity and high gain Folded Cascode LNA for narrowband receiver applications.
Microelectron. J., 2016

A Low-Power and Highly Linear Merged Low Noise Amplifier-Mixer for Wireless Sensor Network Applications.
J. Low Power Electron., 2016

2015
A 4 bit medium speed flash ADC using inverter based comparator in 0.18μm CMOS.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014
Differential Voltage Mode On-Chip Serial Transceiver for Global Interconnects.
J. Low Power Electron., 2014

2013
System-on-programmable-chip implementation of diminishing learning based pattern recognition system.
Int. J. Mach. Learn. Cybern., 2013

Design of a novel differential on-chip wave-pipelined serial interconnect with surfing.
Microprocess. Microsystems, 2013

A Power Efficient Low Noise Preamplifier for Biomedical Applications.
J. Low Power Electron., 2013

A 1.8V 2.4 GHz Folded-Switch Mixer for Direct Conversion Receiver.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Design of a Biometric Security System Using Support Vector Machine Classifier.
Proceedings of the Intelligent Computing, 2013

2012
An enhanced folded cascode OTA with push pull input stage.
Proceedings of the International Multi-Conference on Systems, Signals & Devices, 2012

2011
A Low Power Reconfigurable Analog Baseband Block for Software Defined Radio.
J. Signal Process. Syst., 2011

Design of a real time automatic speech recognition system using Modified One Against All SVM classifier.
Microprocess. Microsystems, 2011

Hardware Implementation of Real-Time Speech Recognition System Using TMS320C6713 DSP.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

2010
Study and evaluation of a multi-class SVM classifier using diminishing learning technique.
Neurocomputing, 2010

Implementation of a Novel Phoneme Recognition System Using TMS320C6713 DSP.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009
Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits.
ACM Trans. Reconfigurable Technol. Syst., 2009

Software/Hardware Co-design of HMM Based Speaker Independent Isolated Digit Recognition System.
J. Comput., 2009

A low power CMOS voltage reference circuit with sub threshold MOSFETs.
Int. J. Inf. Commun. Technol., 2009

Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

100KHz-20MHz Programmable Subthreshold G<sub>m</sub>-C Low-Pass Filter in 0.18µ-m CMOS.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Design of a Modified One-Against-All SVM Classifier.
Proceedings of the IEEE International Conference on Systems, 2009

A Scheduling Policy for Battery Management in Mobile Devices.
Proceedings of the First International Conference on Networks and Communications, 2009

Performance Evaluation of On-Demand Multipath Distance Vector Routing Protocol under Different Traffic Models.
Proceedings of the ARTCom 2009, 2009

Performance Evaluation of Adhoc Networks with Different Multicast Routing Protocols and Mobility Models.
Proceedings of the ARTCom 2009, 2009

2008
VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme.
VLSI Design, 2008

Automation techniques for implementation of hybrid wave-pipelined 2D DWT.
J. Real Time Image Process., 2008

VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition System.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

SOC implementation of wave-pipelined circuits.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2005
Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks.
IEEE Trans. Very Large Scale Integr. Syst., 2005

1997
Queuing analysis of a non-pre-emptive MMPP/D/1 priority system.
Comput. Commun., 1997


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