B. Jhnanesh Somayaji

According to our database¹, B. Jhnanesh Somayaji authored at least 2 papers between 2016 and 2017.

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2017

Triple Reduced Surface Field Drain Extended MOS Device Design and Its RF Performance Evaluation for Sub-Micron RF SoC Platform.

[BibT_eX]

[DOI]

J. Low Power Electron., 2017

2016

Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016