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B. Jayaram

Affiliations:
  • Indian Institute of Technology Madras, Department of Computer Science and Engineering, VLSI Lab, Chennai, India


According to our database1, B. Jayaram authored at least 5 papers between 2003 and 2004.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2004
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays.
[BibTeX]
[DOI]
A. Manoj Kumar
,
B. Jayaram
,
R. Manimegalai
,
V. Kamakoti
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis.
[BibTeX]
[DOI]
R. Manimegalai
,
B. Jayaram
,
A. Manoj Kumar
,
V. Kamakoti
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks.
[BibTeX]
[DOI]
R. Manimegalai
,
A. Manoj Kumar
,
B. Jayaram
,
V. Kamakoti
Proceedings of the Field Programmable Logic and Application, 2004

SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis.
[BibTeX]
[DOI]
A. Manoj Kumar
,
B. Jayaram
,
V. Kamakoti
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003
Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification.
[BibTeX]
[DOI]
B. Jayaram
,
A. Manoj Kumar
,
V. Kamakoti
Proceedings of the High Performance Computing - HiPC 2003, 10th International Conference, 2003


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