Azeez Bhavnagarwala

According to our database, Azeez Bhavnagarwala authored at least 12 papers between 1996 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um² 6T bitcell in a 16nm FinFET CMOS process.

Azeez Bhavnagarwala, Imran Iqbal, An Nguyen, David Ondricek, Vikas Chandra, Robert C. Aitken

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2014

Innovative practices session 2C: Advanced in yield learning.

Yen-Tzu Lin, Brady Benware, Brian Stine, Azeez Bhavnagarwala

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

2010

The semiconductor industry in 2025.

Azeez Bhavnagarwala, Shekhar Borkar, Takayasu Sakurai, Siva G. Narendra

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing.

Azeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler

IEEE J. Solid State Circuits, 2008

2003

Low-power circuits and technology for wireless digital systems.

Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban

IBM J. Res. Dev., 2003

2002

Analysis of the effect of the gate oxide breakdown on SRAM stability.

Rosana Rodríguez, James H. Stathis, Barry P. Linder, Steven P. Kowalczyk, Ching-Te Chuang, Rajiv V. Joshi, Gregory A. Northrop, Kerry Bernstein, Azeez J. Bhavnagarwala, Salvatore Lombardo

Microelectron. Reliab., 2002

2001

The impact of intrinsic device fluctuations on CMOS SRAM cell stability.

Azeez J. Bhavnagarwala, Xinghai Tang, James D. Meindl

IEEE J. Solid State Circuits, 2001

Interconnect-centric Array Architectures for Minimum SRAM Access Time.

Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000

A minimum total power methodology for projecting limits on CMOS GSI.

Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl

IEEE Trans. Very Large Scale Integr. Syst., 2000

CMOS system-on-a-chip voltage scaling beyond 50nm.

Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1998

Minimum supply voltage for bulk Si CMOS GSI.

Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1996

Circuit techniques for low-power CMOS GSI.

Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996