Azam Seyedi

According to our database, Azam Seyedi authored at least 10 papers between 2011 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements.

Azam Seyedi, Snorre Aunet, Per Gunnar Kjeldsberg

IEEE Access, 2022

2019

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications.

Azam Seyedi, Snorre Aunet, Per Gunnar Kjeldsberg

Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

2016

Circuit designs for increasing reliability and reducing energy.

Azam Seyedi

PhD thesis, 2016

2015

NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs.

Azam Seyedi, Vasileios Karakostas, Stefan Cosemans, Adrián Cristal, Mario Nemirovsky, Osman S. Unsal

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

2014

Flexicache: Highly Reliable and Low Power Cache under Supply Voltage Scaling.

Gulay Yalcin, Azam Seyedi, Osman S. Unsal, Adrián Cristal

Proceedings of the High Performance Computing - First HPCLATAM, 2014

2013

Circuit design of a novel adaptable and reliable L1 data cache.

Azam Seyedi, Gulay Yalcin, Osman S. Unsal, Adrián Cristal

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Circuit design of a dual-versioning L1 data cache.

Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero

Integr., 2012

Novel SRAM bias control circuits for a low power L1 data cache.

Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Mateo Valero

Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

2011

Circuit design of a dual-versioning L1 data cache for optimistic concurrency.

Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.

Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011