Azadeh Alsadat Emrani Zarandi

According to our database, Azadeh Alsadat Emrani Zarandi authored at least 15 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

An efficient multi-format low-precision floating-point multiplier.

Hadis Ahmadpour Kermani, Azadeh Alsadat Emrani Zarandi

Sustain. Comput. Informatics Syst., January, 2024

2023

uLog: a software-based approximate logarithmic number system for computations on SIMD processors.

Saeedeh Jahanshahi, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi

J. Supercomput., 2023

2022

Effect of the Spectrum Sensing Period on the TCP Performance Over Cognitive Radio Ad-hoc Networks.

Mohammad Mehdi Hassani, Sanaz Pashmforoush, Azadeh Alsadat Emrani Zarandi

Wirel. Pers. Commun., 2022

Low-Precision Floating-Point Formats: From General-Purpose to Application-Specific.

Amir Sabbagh Molahosseini, Leonel Sousa, Azadeh Alsadat Emrani Zarandi, Hans Vandierendonck

Proceedings of the Approximate Computing, 2022

2021

Variable Latency Carry Speculative Adders with Input-based Dynamic Configuration.

Hoda Ghabeli, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa

Comput. Electr. Eng., 2021

A Multifunctional Unit For Reverse Conversion and Sign Detection Based on The 5-Moduli Set.

Mohsen Mojahed, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi

Comput. Sci., 2021

2019

Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding.

Fereshteh Jafarzadehpour, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa

IEEE Trans. Very Large Scale Integr. Syst., 2019

New energy-efficient hybrid wide-operand adder architecture.

Fereshteh Jafarzadehpour, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa

IET Circuits Devices Syst., 2019

2018

Towards Efficient Modular Adders based on Reversible Circuits.

Amir Sabbagh Molahosseini, Ailin Asadpoor, Azadeh Alsadat Emrani Zarandi, Leonel Sousa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2^k, 2^P-1}.

Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini, Leonel Sousa, Mehdi Hosseinzadeh

IEEE Trans. Very Large Scale Integr. Syst., 2017

A Multifunctional Unit for Designing Efficient RNS-Based Datapaths.

Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Paulo Martins, Leonel Sousa

IEEE Access, 2017

2016

Area-delay-power-aware adder placement method for RNS reverse converter design.

Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini, Leonel Sousa, Mehdi Hosseinzadeh, Keivan Navi

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015

Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations.

Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini, Mehdi Hosseinzadeh, Saeid Sorouri, Samuel Antão, Leonel Sousa

IEEE Trans. Very Large Scale Integr. Syst., 2015

2014

Rethinking reverse converter design: From algorithms to hardware components.

Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Seyed Mostafa Mirhosseini, Mehdi Hosseinzadeh

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2012

MSDP with ACO: A maximal SRLG disjoint routing algorithm based on ant colony optimization.

Mohammad Javad Rostami, Azadeh Alsadat Emrani Zarandi, Seyed Mohamad Hoseininasab

J. Netw. Comput. Appl., 2012