Ayuka Morioka

According to our database, Ayuka Morioka authored at least 7 papers between 2013 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

NanoBridge-Based FPGA in High-Temperature Environments.

Makoto Miyamura, Toshitsugu Sakamoto, Xu Bai, Yukihide Tsuji, Ayuka Morioka, Ryusuke Nebashi, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada, Tadahiko Sugibayashi, Yuya Nagamatsu, Soichi Ookubo, Takuma Shirai, Fumihito Sugai, Masayuki Inaba

IEEE Micro, 2017

2016

A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond.

Yukihide Tsuji, Xu Bai, Ayuka Morioka, Makoto Miyamura, Ryusuke Nebashi, Toshitsugu Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada, Tadahiko Sugibayashi

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEEE J. Solid State Circuits, 2015

Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics (Abstract Only).

Xu Bai, Yukihide Tsuji, Ayuka Morioka, Makoto Miyamura, Toshi Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications.

Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.

Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013