Ayoub Sadeghi

According to our database, Ayoub Sadeghi authored at least 14 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

High-efficient and error-resilient gate diffusion input-based approximate full adders for complex multistage rapid structures.

Nabiollah Shiri, Ayoub Sadeghi, Mahmood Rafiee

Comput. Electr. Eng., July, 2023

High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures.

Ayoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri

IEEE Embed. Syst. Lett., March, 2023

Voltage over-scaling CNT-based 8-bit multiplier by high-efficient GDI-based counters.

Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Abdolreza Darabi, Ebrahim Abiri

IET Comput. Digit. Tech., January, 2023

Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits.

Ayoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri

Frontiers Inf. Technol. Electron. Eng., 2023

2022

An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending.

Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Mahsa Tahghigh

Frontiers Inf. Technol. Electron. Eng., 2022

SR-GDI CNTFET-based magnitude comparator for new generation of programmable integrated circuits.

Nabiollah Shiri, Ayoub Sadeghi, Mahmood Rafiee, Maryam Bigonah

Int. J. Circuit Theory Appl., 2022

Tolerant and low power subtractor with 4: 2 compressor and a new TG-PTL-float full adder cell.

Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Rahim Ghayour

IET Circuits Devices Syst., 2022

High-Performance 1-Bit Full Adder With Excellent Driving Capability for Multistage Structures.

Mahmood Rafiee, Nabiollah Shiri, Ayoub Sadeghi

IEEE Embed. Syst. Lett., 2022

Low-Power and Fast-Swing-Restoration GDI-Based Magnitude Comparator for Digital Images Processing.

Mahmood Rafiee, Nabiollah Shiri, Ayoub Sadeghi, Abdolreza Darabi, Ebrahim Abiri

Circuits Syst. Signal Process., 2022

2021

An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications.

Mahmood Rafiee, Farshad Pesaran, Ayoub Sadeghi, Nabiollah Shiri

Microelectron. J., 2021

2020

High-Efficient, Ultra-Low-Power and High-Speed 4: 2 Compressor with a New Full Adder Cell for Bioelectronics Applications.

Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee

Circuits Syst. Signal Process., 2020

Optimized Gate Diffusion Input Method-Based Reversible Magnitude Arithmetic Unit Using Non-dominated Sorting Genetic Algorithm II.

Ebrahim Abiri, Abdolreza Darabi, Mohammad Reza Salehi, Ayoub Sadeghi

Circuits Syst. Signal Process., 2020

A low-power pseudo-dynamic full adder cell for image addition.

Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Parisa Rahimi

Comput. Electr. Eng., 2020

2019

Gate-diffusion input (GDI) method for designing energy-efficient circuits in analogue voltage-mode fuzzy and QCA systems.

Ebrahim Abiri, Abdolreza Darabi, Ayoub Sadeghi

Microelectron. J., 2019