Ayman Hroub

Orcid: 0009-0004-8023-6052

According to our database1, Ayman Hroub authored at least 10 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Energy Efficient and Fast CNN Inference by Exploring Weight Approximation and Computational Reuse.
IEEE Trans. Artif. Intell., June, 2024

Accelerating memory and I/O intensive HPC applications using hardware compression.
J. Parallel Distributed Comput., 2024

SystemVerilog-SystemC TestBench Architecture for VLSI Chip Design Verification.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

2023
Efficient CNN Hardware Architecture Based on Linear Approximation and Computation Reuse Technique.
Proceedings of the International Conference on Microelectronics, 2023

AUTG: An Automatic UVM-based TestBench Generator for VLSI Chip Design Verification.
Proceedings of the International Conference on Microelectronics, 2023

2022
SecSoC: A Secure System on Chip Architecture for IoT Devices.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2017
A Very Fast Trace-Driven Simulation Platform for Chip-Multiprocessors Architectural Explorations.
IEEE Trans. Parallel Distributed Syst., 2017

Efficient Generation of Compact Execution Traces for Multicore Architectural Simulations.
ACM Trans. Archit. Code Optim., 2017

2015
Towards a Test Definition Language for Integrated Circuits.
J. Circuits Syst. Comput., 2015

Empirical investigation of the challenges of the existing tools used in global software development projects.
IET Softw., 2015


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