Ayan Mandal

Orcid: 0000-0002-0780-3864

According to our database1, Ayan Mandal authored at least 13 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
CABARRE: Request Response Arbitration for Shared Cache Management.
ACM Trans. Embed. Comput. Syst., October, 2023

Dove: Shoulder-Based Opioid Overdose Detection and Reversal Device.
Proceedings of the IEEE/ACM Conference on Connected Health: Applications, 2023

2013
A low-jitter phase-locked resonant clock generation and distribution scheme.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

A source-synchronous Htree-based network-on-chip.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Exploring topologies for source-synchronous ring-based network-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFT.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Alleviating NBTI-induced failure in off-chip output drivers.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

A fast, source-synchronous ring-based network-on-chip design.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Boolean satisfiability using noise based logic.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

An Automated Approach for Minimum Jitter Buffered H-Tree Construction.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

2010
A Hardware Scheduler for Real Time Multiprocessor System on Chip.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010


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