Awinash Anand

According to our database, Awinash Anand authored at least 5 papers between 2011 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

A 1.9GHz Low-Phase-Noise Complementary Cross-Coupled FBAR-VCO without Additional Voltage Headroom in 0.18µm CMOS Technology.

Guoqiang Zhang, Awinash Anand, Kousuke Hikichi, Shuji Tanaka, Masayoshi Esashi, Ken-ya Hashimoto, Shinji Taniguchi, Ramesh K. Pokharel

IEICE Trans. Electron., 2017

2013

Low Phase Noise 14-Bit Digitally Controlled CMOS Quadrature Ring Oscillator.

Ramesh K. Pokharel, Prapto Nugroho, Awinash Anand, Abhishek Tomar, Haruichi Kanaya, Keiji Yoshida

IEICE Trans. Electron., 2013

2012

Analytical method to determine optimal out-of-band gain in multi-bit delta-sigma modulator.

Awinash Anand, Nischal Koirala, Ramesh K. Pokharel, Haruichi Kanaya, Keiji Yoshida

IEICE Electron. Express, 2012

2011

A Wide Tuning Range CMOS Quadrature Ring Oscillator with Improved FoM for Inductorless Reconfigurable PLL.

Ramesh K. Pokharel, Shashank Lingala, Awinash Anand, Prapto Nugroho, Abhishek Tomar, Haruichi Kanaya, Keiji Yoshida

IEICE Trans. Electron., 2011

A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS.

Ghazal A. Fahmy, Daisuke Kanemoto, Haruichi Kanaya, Keiji Yoshida, Ramesh K. Pokharel, Awinash Anand

IEICE Electron. Express, 2011