Awais Sani
According to our database1,
Awais Sani
authored at least 11 papers
between 2010 and 2016.
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Bibliography
2016
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
In-place memory mapping approach for optimized parallel hardware interleaver architectures.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures.
Proceedings of the IEEE International Conference on Acoustics, 2014
2013
A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm.
IEEE Trans. Signal Process., 2013
On-chip implementation of memory mapping algorithm to support flexible decoder architecture.
Proceedings of the IEEE International Conference on Acoustics, 2013
2012
A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
2011
An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Design and analysis of fuzzy logic based robust PID controller for PWM-based switching converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A methodology based on Transportation problem modeling for designing parallel interleaver architectures.
Proceedings of the IEEE International Conference on Acoustics, 2011
2010
Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach.
Proceedings of the 17th IEEE International Conference on Electronics, 2010