Avishek Sinha Roy

According to our database, Avishek Sinha Roy authored at least 7 papers between 2012 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

ACBAM-Accuracy-Configurable Sign Inclusive Broken Array Booth Multiplier Design.

Avishek Sinha Roy, Hardik Agrawal, Anindya Sundar Dhar

IEEE Trans. Emerg. Top. Comput., 2022

2020

On Fast and Exact Computation of Error Metrics in Approximate LSB Adders.

Avishek Sinha Roy, Rajdeep Biswas, Anindya Sundar Dhar

IEEE Trans. Very Large Scale Integr. Syst., 2020

SIBAM - Sign Inclusive Broken Array Multiplier Design for Error Tolerant Applications.

Avishek Sinha Roy, Anindya Sundar Dhar

IEEE Trans. Circuits Syst., 2020

A Low-Error, Memory-Based Fast Binary Logarithmic Converter.

Biswabandhu Jana, Avishek Sinha Roy, Goutam Saha, Swapna Banerjee

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2018

A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders.

Avishek Sinha Roy, Anindya Sundar Dhar

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016

Approximate conditional carry adder for error tolerant applications.

Avishek Sinha Roy, N. Prasad, Anindya Sundar Dhar

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2012

Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors.

Debaprasad Das, Avishek Sinha Roy, Hafizur Rahaman

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012