Aviral Shrivastava
Orcid: 0000-0002-1075-897X
According to our database1,
Aviral Shrivastava
authored at least 177 papers
between 2000 and 2024.
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Bibliography
2024
Cooperative Driving of Connected Autonomous vehicle using Responsibility Sensitive Safety Rules: A Control Barrier Functions Approach.
ACM Trans. Cyber Phys. Syst., July, 2024
IEEE Trans. Intell. Veh., January, 2024
IEEE Trans. Computers, January, 2024
IEEE Internet Things Mag., January, 2024
IEEE Trans. Dependable Secur. Comput., 2024
CONClave - Secure and Robust Cooperative Perception for CAVs Using Authenticated Consensus and Trust Scoring.
CoRR, 2024
IncidentNet: Traffic Incident Detection, Localization and Severity Estimation with Sparse Sensing.
CoRR, 2024
Adversarial Defense on Harmony: Reverse Attack for Robust AI Models Against Adversarial Attacks.
IEEE Access, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Conclave - Secure and Robust Cooperative Perception for Connected Autonomous Vehicle Using Authenticated Consensus and Trust Scoring.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Proceedings of the International Conference on Compilers, 2024
2023
ACM Trans. Embed. Comput. Syst., October, 2023
ACM Trans. Embed. Comput. Syst., 2023
A run-time verification method with consideration of uncertainties for cyber-physical systems.
Microprocess. Microsystems, 2023
CoRR, 2023
Proceedings of the Sixth Conference on Machine Learning and Systems, 2023
Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Explainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
ACM Trans. Cyber Phys. Syst., 2022
EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults.
ACM Trans. Archit. Code Optim., 2022
Real Time Syst., 2022
Root cause analysis of soft-error-induced failures from hardware and software perspectives.
J. Syst. Archit., 2022
Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
Accurate Cooperative Sensor Fusion by Parameterized Covariance Generation for Sensing and Localization Pipelines in CAVs.
Proceedings of the 25th IEEE International Conference on Intelligent Transportation Systems, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
ACM Trans. Cyber Phys. Syst., 2021
ACM Trans. Archit. Code Optim., 2021
Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights.
Proc. IEEE, 2021
Cooperative driving of connected autonomous vehicles using responsibility-sensitive safety (RSS) rules.
Proceedings of the ICCPS '21: ACM/IEEE 12th International Conference on Cyber-Physical Systems, 2021
Comprehensive Failure Analysis against Soft Errors from Hardware and Software Perspectives.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
CHITIN: A Comprehensive In-thread Instruction Replication Technique Against Transient Faults.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Introduction to the Special Issue on Languages, Compilers, Tools, and Theory of Embedded Systems: Part 2.
ACM Trans. Embed. Comput. Syst., 2020
Introduction to the Special Issue on Languages, Compilers, Tools, and Theory of Embedded Systems: Part 1.
ACM Trans. Embed. Comput. Syst., 2020
A Smartphone-Based Passenger Assistant for Public Bus Commute in Developing Countries.
IEEE Trans. Comput. Soc. Syst., 2020
ACM Trans. Cyber Phys. Syst., 2020
Crossroads+: A Time-aware Approach for Intersection Management of Connected Autonomous Vehicles.
ACM Trans. Cyber Phys. Syst., 2020
CRIMSON: Compute-Intensive Loop Acceleration by Randomized Iterative Modulo Scheduling and Optimized Mapping on CGRAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
R<sup>2</sup> IM- Robust and Resilient Intersection Management of Connected Autonomous Vehicles.
Proceedings of the 23rd IEEE International Conference on Intelligent Transportation Systems, 2020
Scaling of Union of Intersections for Inference of Granger Causal Networks from Observational Data.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
2019
ACM Trans. Embed. Comput. Syst., 2019
ACM Trans. Embed. Comput. Syst., 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Encoding and monitoring responsibility sensitive safety rules for automated vehicles in signal temporal logic.
Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
A software-level Redundant MultiThreading for Soft/Hard Error Detection and Recovery.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
A Dependable Detection Mechanism for Intersection Management of Connected Autonomous Vehicles (Interactive Presentation).
Proceedings of the Workshop on Autonomous Systems Design, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
A Compiler Technique for Processor-Wide Protection From Soft Errors in Multithreaded Environments.
IEEE Trans. Reliab., 2018
IEEE Trans. Multi Scale Comput. Syst., 2018
Optimizing the Union of Intersections LASSO (UoI<sub>LASSO</sub>) and Vector Autoregressive (UoI<sub>VAR</sub>) Algorithms for Improved Statistical Estimation at Scale.
CoRR, 2018
Proceedings of the 2018 IEEE Real-Time Systems Symposium, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability.
IEEE Trans. Very Large Scale Integr. Syst., 2017
ACM Trans. Embed. Comput. Syst., 2017
ACM Trans. Embed. Comput. Syst., 2017
ACM Trans. Embed. Comput. Syst., 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
IET Comput. Digit. Tech., 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Margdarshak: A Mobile Data Analytics based Commute Time Estimator cum Route Recommender.
Proceedings of the 3rd International on Workshop on Physical Analytics, 2016
Proceedings of the Second International Symposium on Memory Systems, 2016
Proceedings of the 35th Annual IEEE International Conference on Computer Communications, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 24th ACM SIGSPATIAL International Conference on Advances in Geographic Information Systems, GIS 2016, Burlingame, California, USA, October 31, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016
2015
Efficient Code Assignment Techniques for Local Memory on Software Managed Multicores.
ACM Trans. Embed. Comput. Syst., 2015
A predictable and command-level priority-based DRAM controller for mixed-criticality systems.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015
Towards a reconfigurable distributed testbed to enable advanced research and development of timing and synchronization in cyber-physical systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 2015 International Conference on Compilers, 2015
2014
IEEE Trans. Parallel Distributed Syst., 2014
Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Construction of GCCFG for inter-procedural optimizations in Software Managed Manycore (SMM) architectures.
Proceedings of the 2014 International Conference on Compilers, 2014
2013
Enabling energy efficient reliability in embedded systems through smart cache cleaning.
ACM Trans. Design Autom. Electr. Syst., 2013
ACM Trans. Embed. Comput. Syst., 2013
ACM Trans. Embed. Comput. Syst., 2013
A software-only scheme for managing heap data on limited local memory(LLM) multicore processors.
ACM Trans. Embed. Comput. Syst., 2013
Automatic and efficient heap data management for limited local memory multicore architectures.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs).
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
ACM Trans. Embed. Comput. Syst., 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
Memory access optimization in compilation for coarse-grained reconfigurable architectures.
ACM Trans. Design Autom. Electr. Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Fast and energy-efficient constant-coefficient FIR filters using residue number system.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the International Conference on Parallel Processing, 2011
Proceedings of the International Conference on Parallel Processing, 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
Smart cache cleaning: energy efficient vulnerability reduction in embedded processors.
Proceedings of the 14th International Conference on Compilers, 2011
Proceedings of the 14th International Conference on Compilers, 2011
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Partitioning techniques for partially protected caches in resource-constrained embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2010
A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems.
Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, 2010
Cache vulnerability equations for protecting data in embedded processor caches from soft errors.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010
Proceedings of the High Performance Embedded Architectures and Compilers, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
2009
A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Exploiting residue number system for power-efficient digital signal processing in embedded processors.
Proceedings of the 2009 International Conference on Compilers, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach.
Proceedings of the 16th International Conference on Multimedia 2008, 2008
Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures.
Proceedings of the Distributed Embedded Systems: Design, 2008
SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories.
Proceedings of the High Performance Computing, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Robust Localization in Wireless Sensor Networks through the Revocation of Malicious Anchors.
Proceedings of IEEE International Conference on Communications, 2007
Interactive presentation: Functional and timing validation of partially bypassed processor pipelines.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Smart driver for power reduction in next generation bistable electrophoretic display technology.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Compiler Aided Design of Embedded Computers.
Proceedings of the Compiler Design Handbook: Optimizations and Machine Code Generation, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
ACM Trans. Design Autom. Electr. Syst., 2006
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs.
ACM Trans. Design Autom. Electr. Syst., 2006
Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006
Automatic generation of operation tables for fast exploration of bypasses in embedded processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Mitigating soft error failures for multimedia applications by selective data protection.
Proceedings of the 2006 International Conference on Compilers, 2006
2005
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors.
Proceedings of the 2005 Design, 2005
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Compilation techniques for energy reduction in horizontally partitioned cache architectures.
Proceedings of the 2005 International Conference on Compilers, 2005
2004
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA).
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2002
A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design .
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs.
Proceedings of the 2002 Design, 2002
2000
Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000