Avinoam Kolodny
Affiliations:- Technion - Israel Institute of Technology, Haifa, Israel
According to our database1,
Avinoam Kolodny
authored at least 100 papers
between 2003 and 2019.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2016, "For contributions to VLSI design and automation tools".
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Online presence:
On csauthors.net:
Bibliography
2019
IEEE J. Sel. Areas Commun., 2019
2017
IEEE Comput. Archit. Lett., 2017
2016
J. Parallel Distributed Comput., 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Neural Networks Learn. Syst., 2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing.
Integr., 2015
Integr., 2015
2014
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Microprocess. Microsystems, 2014
IEEE J. Sel. Areas Commun., 2014
Proceedings of the 22nd IEEE Annual Symposium on High-Performance Interconnects, 2014
2013
ACM Trans. Embed. Comput. Syst., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks.
Integr., 2013
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Dynamic traffic distribution among hierarchy levels in hierarchical Networks-on-Chip (NoCs).
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
ACM Trans. Archit. Code Optim., 2012
Microelectron. J., 2012
J. Comb. Optim., 2012
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Distributed adaptive routing for big-data applications running on data center networks.
Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2012
2011
Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints.
VLSI Design, 2011
J. Parallel Distributed Comput., 2011
Proceedings of the NOCS 2011, 2011
An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Proceedings of the Low Power Networks-on-Chip., 2011
2010
Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696].
IEEE Trans. Very Large Scale Integr. Syst., 2010
Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors.
Proceedings of the Third International Symposium on Parallel Architectures, 2010
Interconnect power and delay optimization by dynamic programming in gridded design rules.
Proceedings of the 2010 International Symposium on Physical Design, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the High Performance Embedded Architectures and Compilers, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
ACM Trans. Design Autom. Electr. Syst., 2009
IEEE Comput. Archit. Lett., 2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2008
ACM Trans. Design Autom. Electr. Syst., 2008
IEEE Comput. Archit. Lett., 2008
Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008
2007
VLSI Design, 2007
IEEE Comput. Archit. Lett., 2007
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Maximum effective distance of on-chip decoupling capacitors in power distribution grids.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
2005
Comparison of Sigma-delta Converter Circuit Architectures in Digital Cmos Technology.
J. Circuits Syst. Comput., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
J. Syst. Archit., 2004
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004
Proceedings of the 2004 International Symposium on System-on-Chip, 2004
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects.
Proceedings of the IFIP VLSI-SoC 2003, 2003