Avinash Karanth

IEEE Trans. Parallel Distributed Syst., January, 2024

Editorial: EiC Farewell and Introduction of new EiC.

[BibT_eX]

[DOI]

IEEE Trans. Computers, January, 2024

Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults.

[BibT_eX]

[DOI]

CoRR, 2024

SCORCH: Neural Architecture Search and Hardware Accelerator Co-design with Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

PCM Enabled Low-Power Photonic Accelerator for Inference and Training on Edge Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

HSCONN: Hardware-Software Co-Optimization of Self-Attention Neural Networks for Large Language Models.

[BibT_eX]

[DOI]

Prakash Chand Kuve

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

SNAC: Mitigation of Snoop-Based Attacks with Multi-Tier Security in NoC Architectures.

[BibT_eX]

[DOI]

Saumya Chauhan

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

d-GUARD: Thwarting Denial-of-Service Attacks via Hardware Monitoring of Information Flow using Language Semantics in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Reclaimer: A Reinforcement Learning Approach to Dynamic Resource Allocation for Cloud Microservices.

[BibT_eX]

[DOI]

CoRR, 2023

Reflections of Cybersecurity Workshop for K-12 Teachers.

[BibT_eX]

[DOI]

Chad Mourning

Harsha Chenji

Allyson Hallman-Thrasher

Proceedings of the 54th ACM Technical Symposium on Computer Science Education, Volume 1, 2023

DAGGER: Exploiting Language Semantics for Program Security in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Flumen: Dynamic Processing in the Photonic Interconnect.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

A Silicon Photonic Multi-DNN Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022

SPRINT: A High-Performance, Energy-Efficient, and Scalable Chiplet-Based Accelerator With Photonic Interconnects for CNN Inference.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2022

HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip Architecture.

[BibT_eX]

[DOI]

Padmaja Bhamidipati

IEEE Trans. Emerg. Top. Comput., 2022

Exploiting Wireless Technology for Energy-Efficient Accelerators With Multiple Dataflows and Precision.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Reflections of Cybersecurity Workshop for K-12 Teachers and High School Students.

[BibT_eX]

[DOI]

Chad Mourning

David Juedes

Allyson Hallman-Thrasher

Harsha Chenji

Savas Kaya

Proceedings of the SIGCSE 2022: The 53rd ACM Technical Symposium on Computer Science Education, 2022

SPACX: Silicon Photonics-based Scalable Chiplet Accelerator for DNN Inference.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021

Albireo: Energy-Efficient Acceleration of Convolutional Neural Networks via Silicon Photonics.

[BibT_eX]

[DOI]

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

WiNN: Wireless Interconnect based Neural Network Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

CSCNN: Algorithm-hardware Co-design for CNN Accelerators using Centrosymmetric Filters.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Dynamic Voltage and Frequency Scaling to Improve Energy-Efficiency of Hardware Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on High Performance Computing, 2021

Bitwise Neural Network Acceleration Using Silicon Photonics.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Guest Editors' Introduction to the Special Issue on Machine Learning Architectures and Accelerators.

[BibT_eX]

[DOI]

Xuehai Qian

Yanzhi Wang

IEEE Trans. Computers, 2020

Reconfigurable Gates with Sub-10nm Ambipolar SB-FinFETs for Logic Locking & Obfuscation.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage Regulators using Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020

4-Input NAND and NOR Gates Based on Two Ambipolar Schottky Barrier FinFETs.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

PIXEL: Photonic Neural Network Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019

Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Sustain. Comput., 2019

Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs.

[BibT_eX]

[DOI]

Jacques Henri Collet

ACM J. Emerg. Technol. Comput. Syst., 2019

IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores.

[BibT_eX]

[DOI]

Proceedings of the 46th International Symposium on Computer Architecture, 2019

High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

GARUDA: Designing Energy-Efficient Hardware Monitors From High-Level Policies for Secure Information Flow.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Mitigation of Hardware Trojan based Denial-of-Service attack for secure NoCs.

[BibT_eX]

[DOI]

Avinash Kodi

J. Parallel Distributed Comput., 2018

SHARP: Shared Heterogeneous Architecture with Reconfigurable Photonic Network-on-Chip.

[BibT_eX]

[DOI]

Scott Vanwinkle

ACM J. Emerg. Technol. Comput. Syst., 2018

Securing NoCs Against Timing Attacks with Non-Interference Based Adaptive Routing.

[BibT_eX]

[DOI]

Travis H. Boraten

Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Sub-THz Tunable Push-Push Oscillators with FinFETs for Wireless NoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Scalable Power-Efficient Kilo-Core Photonic-Wireless NoC Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

RETUNES: Reliable and Energy-Efficient Network-on-Chip Architecture.

[BibT_eX]

[DOI]

Padmaja Bhamidipati

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

LEAD: learning-enabled energy-aware dynamic voltage/frequency scaling in NoCs.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Antennas and Channel Characteristics for Wireless Networks on Chips.

[BibT_eX]

[DOI]

Wirel. Pers. Commun., 2017

CLAP-NET: Bandwidth adaptive optical crossbar architecture.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2017

Ultra-compact sub-10nm logic circuits based on ambipolar SB-FinFETs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Machine learning enabled power-aware Network-on-Chip design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Reconfigurable Optical and Wireless (R-OWN) Network-on-Chip for High Performance Computing.

[BibT_eX]

[DOI]

Md. Ashif I. Sikder

Proceedings of the 3rd ACM International Conference on Nanoscale Computing and Communication, 2016

Dynamic error mitigation in NoCs using intelligent prediction techniques.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Mitigation of Denial of Service Attack with Hardware Trojans in NoC Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

Exploring Wireless Technology for Off-Chip Memory Access.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Annual Symposium on High-Performance Interconnects, 2016

Secure Model Checkers for Network-on-Chip (NoC) Architectures.

[BibT_eX]

[DOI]

Dominic DiTomaso

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

An adaptive routing algorithm to improve lifetime reliability in NoCs architecture.

[BibT_eX]

[DOI]

Juman Alshraiedeh

Avinash Kodi

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Packet security with path sensitization for NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

A-WiNoC: Adaptive Wireless Network-on-Chip Architecture for Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2015

A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-clockwise Optical Routing.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

Kilo-core Wireless Network-on-Chips (NoCs) Architectures.

[BibT_eX]

[DOI]

Proceedings of the Second Annual International Conference on Nanoscale Computing and Communication, 2015

OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Annual Symposium on High-Performance Interconnects, 2015

Power and performance analysis of scalable photonic networks for exascale architecture.

[BibT_eX]

[DOI]

Brian Neel

William C. Brantley

Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Cross-Chip: Low power processor-to-memory nanophotonic interconnect architecture.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Dynamic Power Reduction Techniques in On-Chip Photonic Interconnects.

[BibT_eX]

[DOI]

Brian Neel

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Extending the Performance and Energy-Efficiency of Shared Memory Multicores with Nanophotonic Technology.

[BibT_eX]

[DOI]

Evan Jolley

IEEE Trans. Parallel Distributed Syst., 2014

Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Photonic Interconnects for Exascale and Datacenter Architectures.

[BibT_eX]

[DOI]

Brian Neel

William C. Brantley

IEEE Micro, 2014

Workload assignment considering NBTI degradation in multicore systems.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers.

[BibT_eX]

[DOI]

Dominic DiTomaso

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Channel modeling for wireless networks-on-chips.

[BibT_eX]

[DOI]

David W. Matolak

Savas Kaya

IEEE Commun. Mag., 2013

Evaluating the scalability and performance of 3D stacked reconfigurable nanophotonic interconnects.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

PROBE: Prediction-based optical bandwidth scaling for energy-efficient NoCs.

[BibT_eX]

[DOI]

Li Zhou

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Energy-efficient adaptive wireless NoCs architecture.

[BibT_eX]

[DOI]

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

On ultra-short wireless interconnects for NoCs and SoCs: Bridging the 'THz Gap'.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Design of a Concentrated Torus Topology with Channel Buffers and Efficient Crossbars in NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Energy-efficient Runtime Adaptive Scrubbing in fault-tolerant Network-on-Chips (NoCs) architectures.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012

Wireless networks-on-chips: architecture, wireless channel, and devices.

[BibT_eX]

[DOI]

IEEE Wirel. Commun., 2012

SPRINT: Scalable Photonic Switching Fabric for High-Performance Computing (HPC).

[BibT_eX]

[DOI]

JOCN, 2012

Energy efficient modulation for a wireless network-on-chip architecture.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Evaluation and performance analysis of energy efficient wireless NoC architecture.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Evaluation of fault tolerant channel buffers for improving reliability in NoCs.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Energy-Efficient and Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Power efficient photonic networks for many-core architectures.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Green Computing Conference, 2012

2011

Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture.

[BibT_eX]

[DOI]

Yixuan Zhang

Randy Wayne Morris Jr.

Microprocess. Microsystems, 2011

Introduction to the special issue on Networks-on-Chip (NoC) of the Journal of Parallel and Distributed Computing (JPDC).

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2011

Co-design of channel buffers and crossbar organizations in NoCs architectures.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE 19th Annual Symposium on High Performance Interconnects, 2011

2010

Special Issue on Network-on-Chips (NoCs).

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2010

Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores.

[BibT_eX]

[DOI]

Randy Wayne Morris Jr.

Proceedings of the NOCS 2010, 2010

Workload capacity considering NBTI degradation in multi-core systems.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

On-Chip photonic interconnects for scalable multi-core architectures.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

NBTI aware workload balancing in multi-core systems.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs).

[BibT_eX]

[DOI]

Janet Meiling Wang

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Design of a scalable nanophotonic interconnect for future multicores.

[BibT_eX]

[DOI]

Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009

2008

Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis.

[BibT_eX]

[DOI]

Ashwini Sarathy

IEEE Trans. Computers, 2008

Optisim: A System Simulation Methodology for Optically Interconnected HPC Systems.

[BibT_eX]

[DOI]

IEEE Micro, 2008

iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures.

[BibT_eX]

[DOI]

Ashwini Sarathy

Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007

Performance adaptive power-aware reconfigurable optical interconnects for high-performance computing (HPC) systems.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007

Power-Aware Bandwidth-Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems.

[BibT_eX]

[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Implementation of Dynamic Bandwidth Re-allocation in Optical Interconnects using Microring Resonators.

[BibT_eX]

[DOI]

Chander Kochar

Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007

Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture.

[BibT_eX]

[DOI]

Ashwini Sarathy

Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2007

2006

RAPID: Reconfigurable All-Photonic Interconnect for Parallel and Distributed Computers.

[BibT_eX]

[DOI]

PhD thesis, 2006

A New Dynamic Bandwidth Re-Allocation Technique in Optically Interconnected High-Performance Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Symposium on High-Performance Interconnects, 2006

2005

Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors.

[BibT_eX]

[DOI]

IEEE Micro, 2005

2004

An Optical Interconnection Network and a Modified Snooping Protocol for the Design of Large-Scale Symmetric Multiprocessors (SMPs).

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2004

A Scalable Architecture for Distributed Shared Memory Multiprocessors Using Optical Interconnects.

[BibT_eX]

[DOI]