Avijit Dutta
Orcid: 0000-0003-2672-7331Affiliations:
- Institute for Advancing Intelligence, TCG-CREST, Kolkata, India
According to our database1,
Avijit Dutta
authored at least 62 papers
between 2005 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
On csauthors.net:
Bibliography
2024
Des. Codes Cryptogr., January, 2024
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
IACR Commun. Cryptol., 2024
Adv. Math. Commun., 2024
2023
IACR Trans. Symmetric Cryptol., 2023
IACR Cryptol. ePrint Arch., 2023
IACR Cryptol. ePrint Arch., 2023
Adv. Math. Commun., 2023
Proceedings of the Progress in Cryptology - INDOCRYPT 2023, 2023
Proceedings of the Information and Communications Security - 25th International Conference, 2023
Proceedings of the Advances in Cryptology - EUROCRYPT 2023, 2023
2022
IACR Cryptol. ePrint Arch., 2022
IACR Cryptol. ePrint Arch., 2022
Des. Codes Cryptogr., 2022
2021
IACR Trans. Symmetric Cryptol., 2021
2020
IACR Cryptol. ePrint Arch., 2020
IACR Cryptol. ePrint Arch., 2020
IACR Cryptol. ePrint Arch., 2020
Autom. Control. Comput. Sci., 2020
2019
IACR Trans. Symmetric Cryptol., 2019
IACR Cryptol. ePrint Arch., 2019
IACR Cryptol. ePrint Arch., 2019
2018
IACR Trans. Symmetric Cryptol., 2018
IACR Cryptol. ePrint Arch., 2018
2017
IEEE Trans. Computers, 2017
2016
IACR Cryptol. ePrint Arch., 2016
Proceedings of the Information Security and Privacy - 21st Australasian Conference, 2016
2015
IACR Cryptol. ePrint Arch., 2015
2014
Proceedings of the Advances in Information and Computer Security, 2014
2013
Canonical ordering of instances to immunize the FPGA place and route flow from ECO-induced variance.
Proceedings of the International Symposium on Quality Electronic Design, 2013
2012
Low cost adjacent double error correcting code with complete elimination of miscorrection within a dispersion window for Multiple Bit Upset tolerant memory.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
2011
A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores.
Proceedings of the 2011 IEEE International Test Conference, 2011
EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism.
Proceedings of the 2011 IEEE International Test Conference, 2011
2008
Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
2007
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
2005
Synthesis of nonintrusive concurrent error detection using an even error detecting function.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005