Avaneesh K. Dubey

According to our database, Avaneesh K. Dubey authored at least 4 papers between 2018 and 2021.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2021

Design and Performance of High-Speed Energy-Efficient CMOS Double Tail Dynamic Latch Comparator Using GACOBA Load Suitable for Low Voltage Applications.

Vikrant Varshney, Avaneesh K. Dubey, Rajendra Kumar Nagaria

J. Circuits Syst. Comput., 2021

2019

Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect.

Avaneesh K. Dubey, Rajendra Kumar Nagaria

J. Circuits Syst. Comput., 2019

2018

Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load.

Avaneesh K. Dubey, Rajendra Kumar Nagaria

Microelectron. J., 2018

Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique.

Avaneesh K. Dubey, Rajendra Kumar Nagaria

J. Circuits Syst. Comput., 2018