Avaneendra Gupta

According to our database, Avaneendra Gupta authored at least 8 papers between 1996 and 2000.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2000

CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells.

Avaneendra Gupta, John P. Hayes

ACM Trans. Design Autom. Electr. Syst., 2000

1999

Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells.

Avaneendra Gupta, John P. Hayes

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998

Optimal 2-D cell layout with integrated transistor folding.

Avaneendra Gupta, John P. Hayes

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

Integer-programming-based layout synthesis of two-dimensional CMOS cells.

Avaneendra Gupta

PhD thesis, 1997

A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells.

Avaneendra Gupta, John P. Hayes

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells.

Avaneendra Gupta, John P. Hayes

Proceedings of the 34st Conference on Design Automation, 1997

1996

Width minimization of two-dimensional CMOS cells using integer programming.

Avaneendra Gupta, John P. Hayes

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

XPRESS: A Cell Layout Generator with Integrated Transistor Folding.

Avaneendra Gupta, Siang-Chun The, John P. Hayes

Proceedings of the 1996 European Design and Test Conference, 1996