Avadhani Shridhar

According to our database, Avadhani Shridhar authored at least 3 papers between 1996 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1997

Instruction buffering to reduce power in processors for signal processing.

Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki

IEEE Trans. Very Large Scale Integr. Syst., 1997

1996

Interlaced accumulation programming for low power DSP.

Hirotsugu Kojima, Avadhani Shridhar

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer.

Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996