Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2025
CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction.
IEEE J. Solid State Circuits, February, 2025
A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array.
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IEEE J. Solid State Circuits, January, 2025
14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and <<sup>-30</sup> Loss for Compound AI.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling.
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CoRR, 2024
Efficient Orchestrated AI Workflows Execution on Scale-out Spatial Architecture.
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CoRR, 2024
A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Re-Computing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling.
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Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024
15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
34.1 A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models.
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Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture.
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Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization.
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IEEE J. Solid State Circuits, March, 2023
STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
A 28nm 77.35TOPS/W Similar Vectors Traceable Transformer Processor with Principal-Component-Prior Speculating and Dynamic Bit-wise Stationary Computing.
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Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A Systolic Computing-in-Memory Array based Accelerator with Predictive Early Activation for Spatiotemporal Convolutions.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
BR-CIM: An Efficient Binary Representation Computation-In-Memory Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
MC-CIM: a reconfigurable computation-in-memory for efficient stereo matching cost computation.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization.
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Proceedings of the IEEE International Solid-State Circuits Conference, 2021