An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree.
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IEEE Trans. Very Large Scale Integr. Syst., June, 2025
Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge.
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IEEE Trans. Very Large Scale Integr. Syst., February, 2024
Multi-stage Attention Network with Auxiliary Information Refinement for VVC In-loop Filtering.
Proceedings of the IEEE International Conference on Visual Communications and Image Processing, 2024
PFT-ILF: In-loop Filter with Partition Feature Transform for Versatile Video Coding.
Proceedings of the IEEE International Conference on Visual Communications and Image Processing, 2024
34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process.
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Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators.
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Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
PFR-VC: Learning-Based Video Compression Framework with Predicted Frame Refinement.
Proceedings of the International Joint Conference on Neural Networks, 2024
Cross-Frame Integrated Prediction for Feature-Space Video Compression.
Proceedings of the International Joint Conference on Neural Networks, 2024
LIghtweight Texture-Guided Fast Partition Method for Luma and Chroma Intra Coding in VVC.
Proceedings of the IEEE International Conference on Multimedia and Expo, 2024
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference.
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IEEE J. Solid State Circuits, October, 2023